On Sun, Nov 12, 2023 at 09:03:42PM -0000, Roger Sayle wrote:
> This patch improves register pressure during reload, inspired by PR 97756.
> Normally, a double-word right-shift by a constant produces a double-word
> result, the highpart of which is dead when followed by a truncation.
> The dead code calculating the high part gets cleaned up post-reload, so
> the issue isn't normally visible, except for the increased register
> pressure during reload, sometimes leading to odd register assignments.
> Providing a post-reload splitter, which clobbers a single wordmode
> result register instead of a doubleword result register, helps (a bit).
Unfortunately this broke bootstrap on i686-linux, broke all ACATS tests
on x86_64-linux as well as miscompiled e.g. __floattisf in libgcc there
as well.
The bug is that shrd{l,q} instruction expects the low part of the input
to be the same register as the output, rather than the high part as the
patch implemented.
split_double_mode (<DWI>mode, &operands[1], 1, &operands[1], &operands[3]);
sets operands[1] to the lo_half and operands[3] to the hi_half, so if
operands[0] is not the same register as operands[1] (rather than [3]) after
RA, we should during splitting move operands[1] into operands[0].
Your testcase:
> #define MASK60 ((1ul << 60) - 1)
> unsigned long foo (__uint128_t n)
> {
> unsigned long a = n & MASK60;
> unsigned long b = (n >> 60);
> b = b & MASK60;
> unsigned long c = (n >> 120);
> return a+b+c;
> }
still has the same number of instructions.
Bootstrapped/regtested on x86_64-linux (where it e.g. turns
=== acats Summary ===
-# of unexpected failures 2328
+# of expected passes 2328
+# of unexpected failures 0
and fixes gcc.dg/torture/fp-int-convert-*timode.c FAILs as well)
and i686-linux (where it previously didn't bootstrap, but compared to
Friday evening's bootstrap the testresults are ok).
2023-11-14 Jakub Jelinek <jakub@redhat.com>
PR target/112523
PR ada/112514
* config/i386/i386.md (<insn><dwi>3_doubleword_lowpart): Move
operands[1] aka low part of input rather than operands[3] aka high
part of input to output if not the same register.
The r14-5312-g040e5b0edbca861196d9e2ea2af5e805769c8d5d commit log contains
a line from git revert with correct hash, but unfortunately hand ammended
with explanation, so it got through the pre-commit hook but failed during
update_version_git generation. Please don't do this.
2023-11-14 Jakub Jelinek <jakub@redhat.com>
contrib/ChangeLog:
* gcc-changelog/git_update_version.py: Add
040e5b0edb to ignored commits.
libgcc/config/avr/libf7/
* libf7-const.def [F7MOD_sinh_]: Add MiniMax polynomial.
* libf7.c (f7_sinh): Use it instead of (exp(x) - exp(-x)) / 2
when |x| < 0.5 to avoid loss of precision due to cancellation.
Hi,
This little patch adjust the assert in apx-spill_to_egprs-1.c testcase.
The -mapxf compilation option allows more registers to be used, which in
turn eliminates the need for local variables to be stored in stack memory.
Therefore, the assertion is changed to detects no memory loaded through the
%rsp register.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-spill_to_egprs-1.c: Make sure that no local
variables are stored on the stack.
This adds GTY markers to s390_builtin_types, s390_builtin_fn_types,
and s390_builtin_decls. These were missing causing problems in
particular when using builtins after including a precompiled header.
Unfortunately the declaration of these data structures use enum values
from s390-builtins.h. This file however is not included everywhere
and is rather large. In order to include it only for the purpose of
gtype-desc.cc we place a preprocessed copy of it in the build
directory and include only this.
This is going to be backported to GCC 12 and 13.
gcc/ChangeLog:
* config.gcc: Add s390-gen-builtins.h to target_gtfiles.
* config/s390/s390-builtins.h (s390_builtin_types)
(s390_builtin_fn_types, s390_builtin_decls): Add GTY marker.
* config/s390/t-s390 (EXTRA_GTYPE_DEPS): Add s390-gen-builtins.h.
Add build rule for s390-gen-builtins.h.
s390_resolve_overloaded_builtin, when called on NON_DEPENDENT_EXPR,
ICEs when using the type from it which ends up as error_mark_node.
This particular instance of the problem does not occur anymore since
NON_DEPENDENT_EXPR has been removed. Nevertheless that case needs to
be handled here.
gcc/ChangeLog:
* config/s390/s390-c.cc (s390_fn_types_compatible): Add a check
for error_mark_node.
gcc/testsuite/ChangeLog:
* g++.target/s390/zvec-templ-1.C: New test.
Several users have been confused by the status of these warnings,
which can be misunderstood as "this might not be what you want",
rather than diagnostics required by the C++ standard. Add the text "ISO
C++ does not allow" to make this clear.
Also link them to -Wnarrowing so that they can be disabled or promoted
to errors independently of other pedwarns.
PR c++/111842
PR c++/112498
gcc/cp/ChangeLog:
* call.cc (convert_like_internal): Use OPT_Wnarrowing for
pedwarns about illformed conversions involving extended
floating-point types. Clarify that ISO C++ requires these
diagnostics.
gcc/testsuite/ChangeLog:
* g++.dg/cpp23/ext-floating16.C: New test.
* g++.dg/cpp23/ext-floating17.C: New test.
The following patch adds 6 new type-generic builtins,
__builtin_clzg
__builtin_ctzg
__builtin_clrsbg
__builtin_ffsg
__builtin_parityg
__builtin_popcountg
The g at the end stands for generic because the unsuffixed variant
of the builtins already have unsigned int or int arguments.
The main reason to add these is to support arbitrary unsigned (for
clrsb/ffs signed) bit-precise integer types and also __int128 which
wasn't supported by the existing builtins, so that e.g. <stdbit.h>
type-generic functions could then support not just bit-precise unsigned
integer type whose width matches a standard or extended integer type,
but others too.
None of these new builtins promote their first argument, so the argument
can be e.g. unsigned char or unsigned short or unsigned __int20 etc.
The first 2 support either 1 or 2 arguments, if only 1 argument is supplied,
the behavior is undefined for argument 0 like for other __builtin_c[lt]z*
builtins, if 2 arguments are supplied, the second argument should be int
that will be returned if the argument is 0. All other builtins have
just one argument. For __builtin_clrsbg and __builtin_ffsg the argument
shall be any signed standard/extended or bit-precise integer, for the others
any unsigned standard/extended or bit-precise integer (bool not allowed).
One possibility would be to also allow signed integer types for
the clz/ctz/parity/popcount ones (and just cast the argument to
unsigned_type_for during folding) and similarly unsigned integer types
for the clrsb/ffs ones, dunno what is better; for stdbit.h the current
version is sufficient and diagnoses use of the inappropriate sign,
though on the other side I wonder if users won't be confused by
__builtin_clzg (1) being an error and having to write __builtin_clzg (1U).
The new builtins are lowered to corresponding builtins with other suffixes
or internal calls (plus casts and adjustments where needed) during FE
folding or during gimplification at latest, the non-suffixed builtins
handling precisions up to precision of int, l up to precision of long,
ll up to precision of long long, up to __int128 precision lowered to
double-word expansion early and the rest (which must be _BitInt) lowered
to internal fn calls - those are then lowered during bitint lowering pass.
The patch also changes representation of IFN_CLZ and IFN_CTZ calls,
previously they were in the IL only if they are directly supported optab
and depending on C[LT]Z_DEFINED_VALUE_AT_ZERO (...) == 2 they had or didn't
have defined behavior at 0, now they are in the IL either if directly
supported optab, or for the large/huge BITINT_TYPEs and they have either
1 or 2 arguments. If one, the behavior is undefined at zero, if 2, the
second argument is an int constant that should be returned for 0.
As there is no extra support during expansion, for directly supported optab
the second argument if present should still match the
C[LT]Z_DEFINED_VALUE_AT_ZERO (...) == 2 value, but for BITINT_TYPE arguments
it can be arbitrary int INTEGER_CST.
The indended uses in stdbit.h are e.g.
#ifdef __has_builtin
#if __has_builtin(__builtin_clzg) && __has_builtin(__builtin_ctzg) && __has_builtin(__builtin_popcountg)
#define stdc_leading_zeros(value) \
((unsigned int) __builtin_clzg (value, __builtin_popcountg ((__typeof (value)) ~(__typeof (value)) 0)))
#define stdc_leading_ones(value) \
((unsigned int) __builtin_clzg ((__typeof (value)) ~(value), __builtin_popcountg ((__typeof (value)) ~(__typeof (value)) 0)))
#define stdc_first_trailing_one(value) \
((unsigned int) (__builtin_ctzg (value, -1) + 1))
#define stdc_trailing_zeros(value) \
((unsigned int) __builtin_ctzg (value, __builtin_popcountg ((__typeof (value)) ~(__typeof (value)) 0)))
#endif
#endif
where __builtin_popcountg ((__typeof (x)) -1) computes the bit precision
of x's type (kind of _Bitwidthof (x) alternative).
They also allow casting of arbitrary unsigned _BitInt other than
unsigned _BitInt(1) to corresponding signed _BitInt by using
signed _BitInt(__builtin_popcountg ((__typeof (a)) -1))
and of arbitrary signed _BitInt to corresponding unsigned _BitInt
using unsigned _BitInt(__builtin_clrsbg ((__typeof (a)) -1) + 1).
2023-11-14 Jakub Jelinek <jakub@redhat.com>
PR c/111309
gcc/
* builtins.def (BUILT_IN_CLZG, BUILT_IN_CTZG, BUILT_IN_CLRSBG,
BUILT_IN_FFSG, BUILT_IN_PARITYG, BUILT_IN_POPCOUNTG): New
builtins.
* builtins.cc (fold_builtin_bit_query): New function.
(fold_builtin_1): Use it for
BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
(fold_builtin_2): Use it for BUILT_IN_{CLZ,CTZ}G.
* fold-const-call.cc: Fix comment typo on tm.h inclusion.
(fold_const_call_ss): Handle
CFN_BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
(fold_const_call_sss): New function.
(fold_const_call_1): Call it for 2 argument functions returning
scalar when passed 2 INTEGER_CSTs.
* genmatch.cc (cmp_operand): For function calls also compare
number of arguments.
(fns_cmp): New function.
(dt_node::gen_kids): Sort fns and generic_fns.
(dt_node::gen_kids_1): Handle fns with the same id but different
number of arguments.
* match.pd (CLZ simplifications): Drop checks for defined behavior
at zero. Add variant of simplifications for IFN_CLZ with 2 arguments.
(CTZ simplifications): Drop checks for defined behavior at zero,
don't optimize precisions above MAX_FIXED_MODE_SIZE. Add variant of
simplifications for IFN_CTZ with 2 arguments.
(a != 0 ? CLZ(a) : CST -> .CLZ(a)): Use TREE_TYPE (@3) instead of
type, add BITINT_TYPE handling, create 2 argument IFN_CLZ rather than
one argument. Add variant for matching CLZ with 2 arguments.
(a != 0 ? CTZ(a) : CST -> .CTZ(a)): Similarly.
* gimple-lower-bitint.cc (bitint_large_huge::lower_bit_query): New
method.
(bitint_large_huge::lower_call): Use it for IFN_{CLZ,CTZ,CLRSB,FFS}
and IFN_{PARITY,POPCOUNT} calls.
* gimple-range-op.cc (cfn_clz::fold_range): Don't check
CLZ_DEFINED_VALUE_AT_ZERO for m_gimple_call_internal_p, instead
assume defined value at zero if the call has 2 arguments and use
second argument value for that case.
(cfn_ctz::fold_range): Similarly.
(gimple_range_op_handler::maybe_builtin_call): Use op_cfn_clz_internal
or op_cfn_ctz_internal only if internal fn call has 2 arguments and
set m_op2 in that case.
* tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern,
vect_recog_popcount_clz_ctz_ffs_pattern): For value defined at zero
use second argument of calls if present, otherwise assume UB at zero,
create 2 argument .CLZ/.CTZ calls if needed.
* tree-vect-stmts.cc (vectorizable_call): Handle 2 argument .CLZ/.CTZ
calls.
* tree-ssa-loop-niter.cc (build_cltz_expr): Create 2 argument
.CLZ/.CTZ calls if needed.
* tree-ssa-forwprop.cc (simplify_count_trailing_zeroes): Create 2
argument .CTZ calls if needed.
* tree-ssa-phiopt.cc (cond_removal_in_builtin_zero_pattern): Handle
2 argument .CLZ/.CTZ calls, handle BITINT_TYPE, create 2 argument
.CLZ/.CTZ calls.
* doc/extend.texi (__builtin_clzg, __builtin_ctzg, __builtin_clrsbg,
__builtin_ffsg, __builtin_parityg, __builtin_popcountg): Document.
gcc/c-family/
* c-common.cc (check_builtin_function_arguments): Handle
BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
* c-gimplify.cc (c_gimplify_expr): If __builtin_c[lt]zg second
argument hasn't been folded into constant yet, transform it to one
argument call inside of a COND_EXPR which for first argument 0
returns the second argument.
gcc/c/
* c-typeck.cc (convert_arguments): Don't promote first argument
of BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
gcc/cp/
* call.cc (magic_varargs_p): Return 4 for
BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
(build_over_call): Don't promote first argument of
BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
* cp-gimplify.cc (cp_gimplify_expr): For BUILT_IN_C{L,T}ZG use
c_gimplify_expr.
gcc/testsuite/
* c-c++-common/pr111309-1.c: New test.
* c-c++-common/pr111309-2.c: New test.
* gcc.dg/torture/bitint-43.c: New test.
* gcc.dg/torture/bitint-44.c: New test.
As the commit message of r14-4674 has indicated, if the assembler does
not support conditional branch relaxation, a relocation overflow may
happen on conditional branches when relaxation is enabled because the
number of NOP instructions inserted by the assembler will be more than
the number estimated by GCC.
To work around this issue, disable relaxation by default if the
assembler is detected incapable to perform conditional branch relaxation
at GCC build time. We also need to pass -mno-relax to the assembler to
really disable relaxation. But, if the assembler does not support
-mrelax option at all, we should not pass -mno-relax to the assembler or
it will immediately error out. Also handle this with the build time
assembler capability probing, and add a pair of options
-m[no-]pass-mrelax-to-as to allow using a different assembler from the
build-time one.
With this change, if GCC is built with GAS 2.41, relaxation will be
disabled by default. So the default value of -mexplicit-relocs= is also
changed to 'always' if -mno-relax is specified or implied by the
build-time default, because using assembler macros for symbol addresses
produces no benefit when relaxation is disabled.
gcc/ChangeLog:
PR target/112330
* config/loongarch/genopts/loongarch.opt.in: Add
-m[no]-pass-relax-to-as. Change the default of -m[no]-relax to
account conditional branch relaxation support status.
* config/loongarch/loongarch.opt: Regenerate.
* configure.ac (gcc_cv_as_loongarch_cond_branch_relax): Check if
the assembler supports conditional branch relaxation.
* configure: Regenerate.
* config.in: Regenerate. Note that there are some unrelated
changes introduced by r14-5424 (which does not contain a
config.in regeneration).
* config/loongarch/loongarch-opts.h
(HAVE_AS_COND_BRANCH_RELAXATION): Define to 0 if not defined.
* config/loongarch/loongarch-driver.h (ASM_MRELAX_DEFAULT):
Define.
(ASM_MRELAX_SPEC): Define.
(ASM_SPEC): Use ASM_MRELAX_SPEC instead of "%{mno-relax}".
* config/loongarch/loongarch.cc: Take the setting of
-m[no-]relax into account when determining the default of
-mexplicit-relocs=.
* doc/invoke.texi: Document -m[no-]relax and
-m[no-]pass-mrelax-to-as for LoongArch. Update the default
value of -mexplicit-relocs=.
if (TREE_CODE (init_expr) == INTEGER_CST)
init_expr = fold_convert (TREE_TYPE (vectype), init_expr);
else
gcc_assert (tree_nop_conversion_p (TREE_TYPE (vectype),
TREE_TYPE (init_expr)));
and init_expr is a 24 bit integer type while vectype has 32bit components.
The "fix" is to bail out instead of asserting.
gcc/ChangeLog:
PR tree-optimization/112496
* tree-vect-loop.cc (vectorizable_nonlinear_induction): Return
false when !tree_nop_conversion_p (TREE_TYPE (vectype),
TREE_TYPE (init_expr)).
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112496.c: New test.
LA664 defines DBAR hints 0x1 - 0x1f (except 0xf and 0x1f) as follows [1-2]:
- Bit 4: kind of constraint (0: completion, 1: ordering)
- Bit 3: barrier for previous read (0: true, 1: false)
- Bit 2: barrier for previous write (0: true, 1: false)
- Bit 1: barrier for succeeding read (0: true, 1: false)
- Bit 0: barrier for succeeding write (0: true, 1: false)
LLVM has already utilized them for different memory orders [3]:
- Bit 4 is always set to one because it's only intended to be zero for
things like MMIO devices, which are out of the scope of memory orders.
- An acquire barrier is used to implement acquire loads like
ld.d $a1, $t0, 0
dbar acquire_hint
where the load operation (ld.d) should not be reordered with any load
or store operation after the acquire load. To accomplish this
constraint, we need to prevent the load operation from being reordered
after the barrier, and also prevent any following load/store operation
from being reordered before the barrier. Thus bits 0, 1, and 3 must
be zero, and bit 2 can be one, so acquire_hint should be 0b10100.
- An release barrier is used to implement release stores like
dbar release_hint
st.d $a1, $t0, 0
where the store operation (st.d) should not be reordered with any load
or store operation before the release store. So we need to prevent
the store operation from being reordered before the barrier, and also
prevent any preceding load/store operation from being reordered after
the barrier. So bits 0, 2, 3 must be zero, and bit 1 can be one. So
release_hint should be 0b10010.
A similar mapping has been utilized for RISC-V GCC [4], LoongArch Linux
kernel [1], and LoongArch LLVM [3]. So the mapping should be correct.
And I've also bootstrapped & regtested GCC on a LA664 with this patch.
The LoongArch CPUs should treat "unknown" hints as dbar 0, so we can
unconditionally emit the new hints without a compiler switch.
[1]: https://git.kernel.org/torvalds/c/e031a5f3f1ed
[2]: https://github.com/loongson-community/docs/pull/12
[3]: https://github.com/llvm/llvm-project/pull/68787
[4]: https://gcc.gnu.org/r14-406
gcc/ChangeLog:
* config/loongarch/sync.md (mem_thread_fence): Remove redundant
check.
(mem_thread_fence_1): Emit finer-grained DBAR hints for
different memory models, instead of 0.
The following testcase ICEs because BITINT_TYPE isn't handled in
type_contains_placeholder_1. Given that Ada doesn't emit it, it doesn't
matter that much where exactly we handle it as right now it should never
contain a placeholder; I've picked the same spot as INTEGER_TYPE, but if
you prefer e.g. the one with OFFSET_TYPE above, I can move it there too.
2023-11-14 Jakub Jelinek <jakub@redhat.com>
PR middle-end/112511
* tree.cc (type_contains_placeholder_1): Handle BITINT_TYPE like
INTEGER_TYPE.
* gcc.dg/pr112511.c: New test.
The vblendps instruction is only VEX encoded, not EVEX, so can't be used if
there are %ymm16+ or EGPR registers involved.
2023-11-14 Jakub Jelinek <jakub@redhat.com>
Hu, Lin1 <lin1.hu@intel.com>
PR target/112435
* config/i386/sse.md (avx512vl_shuf_<shuffletype>32x4_1<mask_name>,
<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Add
alternative with just x instead of v constraints and xjm instead of
vm and use vblendps as optimization only with that alternative.
* gcc.target/i386/avx512vl-pr112435-1.c: New test.
* gcc.target/i386/avx512vl-pr112435-2.c: New test.
* gcc.target/i386/avx512vl-pr112435-3.c: New test.
analyze_and_compute_bitop_with_inv_effect assumes the first operand is
loop invariant which is not the case when it's INTEGER_CST.
gcc/ChangeLog:
PR tree-optimization/105735
PR tree-optimization/111972
* tree-scalar-evolution.cc
(analyze_and_compute_bitop_with_inv_effect): Handle bitop with
INTEGER_CST.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr105735-3.c: New test.
This patch updates gettext.m4 and related .m4 files and adds
gettext-runtime as a gmp/mpfr/... style host library, allowing newer
libintl to be used.
This patch /does not/ add build-time tools required for
internationalizing (msgfmt et al), instead, it just updates the runtime
library. The result should be a distribution that acts exactly the same
when a copy of gettext is present, and disables internationalization
otherwise.
There should be no changes in behavior when gettext is included in-tree.
When gettext is not included in tree, nor available on the system, the
programs will be built without localization.
ChangeLog:
PR bootstrap/12596
* .gitignore: Add '/gettext*'.
* configure.ac (host_libs): Replace intl with gettext.
(hbaseargs, bbaseargs, baseargs): Split baseargs into
{h,b}baseargs.
(skip_barg): New flag. Skips appending current flag to
bbaseargs.
<library exemptions>: Exempt --with-libintl-{type,prefix} from
target and build machine argument passing.
* configure: Regenerate.
* Makefile.def (host_modules): Replace intl module with gettext
module.
(configure-ld): Depend on configure-gettext.
* Makefile.in: Regenerate.
config/ChangeLog:
* intlmacosx.m4: Import from gettext-0.22 (serial 8).
* gettext.m4: Sync with gettext-0.22 (serial 77).
* gettext-sister.m4 (ZW_GNU_GETTEXT_SISTER_DIR): Load gettext's
uninstalled-config.sh, or call AM_GNU_GETTEXT if missing.
* iconv.m4: Sync with gettext-0.22 (serial 26).
contrib/ChangeLog:
* prerequisites.sha512: Add gettext.
* prerequisites.md5: Add gettext.
* download_prerequisites: Add gettext.
gcc/ChangeLog:
* configure: Regenerate.
* aclocal.m4: Regenerate.
* Makefile.in (LIBDEPS): Remove (potential) ./ prefix from
LIBINTL_DEP.
* doc/install.texi: Document new (notable) flags added by the
optional gettext tree and by AM_GNU_GETTEXT. Document libintl/libc
with gettext dependency.
libcpp/ChangeLog:
* configure: Regenerate.
* aclocal.m4: Regenerate.
libstdc++-v3/ChangeLog:
* configure: Regenerate.
I meant to add these changes as part of r14-4959-g7d06b29f814580 but
missed these files out.
libstdc++-v3/ChangeLog:
* testsuite/std/time/clock/file/io.cc: Double timeout using
dg-timeout-factor.
* testsuite/std/time/clock/gps/io.cc: Likewise.
* testsuite/std/time/clock/local/io.cc: Likewise.
* testsuite/std/time/clock/system/io.cc: Likewise.
* testsuite/std/time/clock/tai/io.cc: Likewise.
* testsuite/std/time/clock/utc/io.cc: Likewise.
This small change removes a branch when clearing a std::optional<T> for
types with no-op destructors. For types where the destructor can be
optimized away (e.g. because it's trivial, or empty and can be inlined)
the _M_destroy() function does nothing but set _M_engaged to false.
Setting _M_engaged=false unconditionally is cheaper than only doing it
when initially true, because it allows the compiler to remove a branch.
The compiler thinks it would be incorrect to unconditionally introduce a
store there, because it could conflict with reads in other threads, so
it won't do that optimization itself. We know it's safe to do because
we're in a non-const member function, so the standard forbids any
potentially concurrent calls to other member functions of the same
object. Making the store unconditional can't create a data race that
isn't already present in the program.
libstdc++-v3/ChangeLog:
PR libstdc++/112480
* include/std/optional (_Optional_payload_base::_M_reset): Set
_M_engaged to false unconditionally.
Flags reg is valid only with CC mode.
gcc/ChangeLog:
* config/i386/i386-expand.h (gen_pushfl): New prototype.
(gen_popfl): Ditto.
* config/i386/i386-expand.cc (ix86_expand_builtin)
[case IX86_BUILTIN_READ_FLAGS]: Use gen_pushfl.
[case IX86_BUILTIN_WRITE_FLAGS]: Use gen_popfl.
* config/i386/i386.cc (gen_pushfl): New function.
(gen_popfl): Ditto.
* config/i386/i386.md (unspec): Add UNSPEC_PUSHFL and UNSPEC_POPFL.
(@pushfl<mode>2): Rename from *pushfl<mode>2.
Rewrite as unspec using UNSPEC_PUSHFL.
(@popfl<mode>1): Rename from *popfl<mode>1.
Rewrite as unspec using UNSPEC_POPFL.
Combine wants to combine following instructions into an insn that can
perform both an (arithmetic) operation and set the condition code. During
the conversion a new RTX is created, and combine passes the RTX code of the
innermost RTX expression of the CC use insn in which CC reg is used to
SELECT_CC_MODE, to determine the new mode of the comparison:
Trying 5 -> 8:
5: r98:DI=0xd7
8: flags:CCZ=cmp(r98:DI,0)
REG_EQUAL cmp(0xd7,0)
Failed to match this instruction:
(parallel [
(set (reg:CC 17 flags)
(compare:CC (const_int 215 [0xd7])
(const_int 0 [0])))
(set (reg/v:DI 98 [ flags ])
(const_int 215 [0xd7]))
])
where:
(insn 5 2 6 2 (set (reg/v:DI 98 [ flags ])
(const_int 215 [0xd7])) "pr112494.c":8:8 84 {*movdi_internal}
(nil))
(insn 8 7 11 2 (set (reg:CCZ 17 flags)
(compare:CCZ (reg/v:DI 98 [ flags ])
(const_int 0 [0]))) "pr112494.c":11:9 8 {*cmpdi_ccno_1}
(expr_list:REG_EQUAL (compare:CCZ (const_int 215 [0xd7])
(const_int 0 [0]))
(nil)))
x86_cc_mode (AKA SELECT_CC_MODE) is not prepared to handle random RTX
codes and triggers gcc_unreachable() when SET RTX code is passed to it.
The patch removes gcc_unreachable() and returns CCmode for unknown
RTX codes, so combine can try various combinations involving CC reg
without triggering ICE.
Please note that x86 MOV instructions do not set flags, so the above
combination is not recognized as a valid x86 instruction.
PR target/112494
gcc/ChangeLog:
* config/i386/i386.cc (ix86_cc_mode) [default]: Return CCmode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112494.c: New test.
bad-mapper-1.C has been failing since the posix_spawn codepath was added
to libiberty, adjust the check to accept the changed error message.
Patch has been verified on x86_64 Linux.
gcc/testsuite:
* g++.dg/modules/bad-mapper-1.C: Also accept posix_spawn.
This patch adds libgm2/acinclude.m4 and libgm2/configure.host which
are reduced versions from libstdc++-v3. They currently allow for
discovering the time features available in libc and will be extended
to discover availability of ieee128 long double support in the near
future. These files were also added to provide the functions:
GLIBCXX_CONFIGURE, GLIBCXX_CHECK_GETTIMEOFDAY and
GLIBCXX_ENABLE_LIBSTDCXX_TIME called by configure.ac.
libgm2/ChangeLog:
PR modula2/110779
* Makefile.in: Regenerate.
* aclocal.m4: Regenerate.
* config.h.in: Regenerate.
* configure: Regenerate.
* configure.ac: Remove newline.
* libm2cor/Makefile.in: Regenerate.
* libm2iso/Makefile.in: Regenerate.
* libm2log/Makefile.in: Regenerate.
* libm2min/Makefile.in: Regenerate.
* libm2pim/Makefile.in: Regenerate.
* acinclude.m4: New file.
* configure.host: New file.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
This test is arm specific and requires neon. To improve compatibility
add a new test for armv7-a with neon and use that.
gcc/testsuite:
* lib/target-supports.exp (v7a_neon): New feature-test target.
* gcc.dg/debug/pr57351.c: Use it.
This fixes a bunch more tests that try to override the default architecture;
some partially used the framework for doing this, others just blindly
added a -march option, which was doomed to cause problems. In most cases
we can now run these tests regardless of the users testing options and
the base compiler configuration.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
Add test for v7a_arm.
* gcc.target/arm/pr60650-2.c: Use require-effective-target and
add-options.
* gcc.target/arm/pr60657.c: Likewise.
* gcc.target/arm/pr60663.c: Likewise.
* gcc.target/arm/pr81863.c: Likewise.
* gcc.target/arm/pr97969.c: Likewise.
* gcc.target/arm/pr98931.c: Likewise.
* gcc.target/arm/tail-long-call.c: Likewise.
Some of the standard Arm architecture tests require the test to use a
specific instruction set (arm or thumb). But although the framework
was checking that the flag was accepted, it wasn't checking that the
flag wasn't somehow being override (eg by run-specific options). We
can improve these tests easily by checking whether or not __thumb-_ is
defined.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
For instruction-set specific tests, check that __thumb__ is, or
isn't defined as appropriate.
Use dg-require-effective-target/dg-add-options to improve
compatibility of this test with various compiler configurations.
gcc/testsuite:
* gcc.target/arm/pr59575.c: Use dg-require-effective-target and
dg-add-options.
Add +fp to the architecture specification, so that -mfpu=auto works
with the hard-float ABI.
gcc/testsuite:
* gcc.target/arm/pr19599.c: Add +fp to the architecture.
These tests deliberately pass invalid option combinations to check
that the compiler is generating the correct diagnostic. Nevertheless,
we can improve their compatibility with other testsuite options. For
optional_thumb-1.c we use a soft-float ABI, while for
optional_thumb2.c we use arm_arch_v7em as the target architecture,
then set the architecture manually.
gcc/testsuite:
* gcc.target/arm/optional_thumb-1.c: Force a soft-float ABI.
* gcc.target/arm/optional_thumb-3.c: Check for armv7e-m compatibility,
then set the architecture explicitly.
Convert these tests to use dg-add-options for increased compatibilty.
Since they also result in an empty translation unit, override the
default testsuite options.
gcc/testsuite:
* gcc.target/arm/macro_defs0.c: Use dg-effective-target and
dg-add-options.
* gcc.target/arm/macro_defs1.c: Likewise.
* gcc.target/arm/macro_defs2.c: Likewise.
This test is specific to armv7m cores which do not support hardware
floating-point. We can improve its compatibility by having the default
options for this core specify -mfloat-abi=soft.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
Use soft-float ABI for armv7m.
* gcc.target/arm/ftest-armv7m-thumb.c: Use dg-require-effective-target
to check flag compatibility.
This test was explicitly setting the architecture on the command-line and
in the body of the test. In both cases this causes problems with the auto
FPU setting. Fix by using the testsuite infrastructure correctly and by
adding +fp to the pragma.
gcc/testsuite:
* gcc.target/arm/pragma_arch_switch_2.c: Use testsuite infrastructure
to set the architecture flags. Add +fp to the pragma that changes the
architecture.
These tests use pragmas adn attributes to change the architecture.
Sometimes they simply add a feature using "+crc", but other times they
try to completely reset the architecture using "arch=armv8-a+crc".
The latter fails on a hard-float ABI with -mfpu=auto because it also
clears the FP capability. Fix by adding +simd when the full
architecture is specified.
gcc/testsuite:
* gcc.target/arm/pragma_arch_attribute.c: Add +simd to pragmas that
set an explicit architecture.
* gcc.target/arm/pragma_arch_attribute_2.c: Likewise.
* gcc.target/arm/pragma_arch_attribute_3.c: Likewise.
Fix another test that was trying to set the architecture directly
rather than using the infrastructure as intended.
gcc/testsuite:
* gcc.target/arm/pr88648-asm-syntax-unified.c: It isn't necessary
to try to override the architecture flags specified by arm_arch_v7a.
Again, use the infrastructure available to improve the compatibility
of these tests.
gcc/testsuite:
* gcc.target/arm/pr78353-1.c: Use dg-add-options to manage target
flags.
* gcc.target/arm/pr78353-2.c: Likewise.
Another case where we can make better use of the infrastructure to
improve the compatibility of this test.
gcc/testsuite:
* gcc.target/arm/pr65647-2.c: Use dg-add-options to manage target
flags.
This test overrides the architecture, but fails to specify the
floating point architecture. This causes problems if -mfpu=auto is
used.
gcc/testsuite:
* gcc.target/arm/lto/pr96939_1.c: Add +simd to the architecture
specification.
gcc.target/arm/g2.c is an xscale-only test, but the test is quite old
and we have improved the infrastructure for setting up such tests now.
So make use of that to reduce the number of cases where this test fails
to run.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
Add entry to check for xscale.
* gcc.target/arm/g2.c: Use it.
This test overrides the architecture, but fails to describe which
floating-point features are needed. This causes problems if the ABI
requires FP for parameter passing and -mfpu=auto is selected, so ensure
that one is specified.
gcc/testsuite:
* gcc.target/arm/attr_thumb-static2.c: Add +fp to the -march
specification.
This test overrides the architecture, but fails to describe which
floating-point features are needed. This causes problems if the ABI
requires FP for parameter passing and -mfpu=auto is selected, so ensure
that one is specified.
gcc/testsuite:
* gcc.target/arm/attr-crypto.c: Add +simd to the -march
specification.
This test overrides the architecture, but fails to describe which
floating-point features are needed. This causes problems if the ABI
requires FP for parameter passing and -mfpu=auto is selected, so ensure
that one is specified.
gcc/testsuite:
* gcc.target/arm/acle/pacbti-m-predef-11.c: Add +fp to the -march
specification.
A number of tests in the gcc testsuite, especially for arm-specific
targets, add various flags to control the architecture. These run
into problems when the compiler is configured with -mfpu=auto if the
new architecture lacks an architectural feature that implies we have
floating-point instructions.
The testsuite makes this worse as it falls foul of this requirement in
the base architecture strings provided by target-supports.exp.
To fix this we add "+fp", or something equivalent to this, to all the
base architecture specifications. The feature will be ignored if the
float ABI is set to soft.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
Add base FPU specifications to all architectures that can support
one.
Add an arm-specific test to check_effective_target_hard_float for
Arm to handle cases where we only have single-precision FP in hardware.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_hard_float): Add
arm-specific test.
Some of the ACLE tests for Arm are executable, but we were only testing
that the compiler could generate code for them, not that the hardware
was capable of executing them. Fix this by adding an execution test for
suitable hardware.
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_arm_arch_v6t2_hw_ok):
New function.
* gcc.target/arm/acle/data-intrinsics-armv6.c: Use it.
* gcc.target/arm/acle/data-intrinsics-rbit.c: Likewise.
