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Author SHA1 Message Date
Christophe Lyon
a064fed18a testsuite: Fix tail_call and musttail effective targets [PR116080] 
Some of the musttail tests (eg musttail7.c) fail on arm-eabi because
check_effective_target_musttail pass, but the actual code in the test
is rejected.

The reason is that on arm-eabi with the default configuration, the
compiler targets armv4t for which TARGET_INTERWORK is true, making
arm_function_ok_for_sibcall reject a tail-call candidate if
TREE_ASM_WRITTEN (decl) is false.

For more recent architecture versions, TARGET_INTERWORK is false,
hence the problem was not seen on all arm configurations.

musttail7.c is in turn rejected because f2 is recursive, so
TREE_ASM_WRITTEN is false.

However, the same code used in check_effective_target_musttail is not
recursive and the function body for foo has TREE_ASM_WRITTEN == true.

The simplest fix is to remove the (empty) body for foo () in
check_effective_target_musttail.  For consistency, do the same with
check_effective_target_tail_call.

gcc/testsuite/ChangeLog:
	PR testsuite/116080
	* lib/target-supports.exp (check_effective_target_tail_call):
	Remove foo's body.
	(check_effective_target_musttail): Likewise.
 2024-11-15 12:56:02 +00:00
Richard Biener
5a2c3a69fb Remove dead code related to VEC_COND_EXPR expansion from ISEL 
ISEL was introduced to translate vector comparison and vector
condition combinations back to internal function calls mapping to
one of the vcond[u][_eq][_mask] and vec_cmp[_eq] optabs.  With
removing the legacy non-mask vcond expanders we now rely on all
vector comparisons and vector conditions to be directly expandable.
The following keeps the intermediate internal function rewrite
given gimple_expand_vec_cond_expr still performs some optimizations
which eventually should move to vector lowering or match.pd, but
simplifies it down to always expand VEC_COND_EXPR to .VCOND_MASK.

	* gimple-isel.cc (gimple_expand_vec_cond_expr): If not
	simplifying or lowering, always expand to .VCOND_MASK.
	(pass_gimple_isel::execute): Simplify.
 2024-11-15 13:42:03 +01:00
Richard Biener
f40010c198 Streamline vector lowering of VEC_COND_EXPR and vector comparisons 
The following makes sure to lower all VEC_COND_EXPRs that we cannot
trivially expand, likewise for comparisons.  In particular no longer
try to combine both in fancy ways.

	* tree-vect-generic.cc (expand_vector_comparison): Lower
	vector comparisons that we cannot trivially expand.  Remove
	code dealing with uses in VEC_COND_EXPRs.
	(expand_vector_condition): Lower vector conditions that we
	cannot trivially expand.  Remove code dealing with comparison
	mask definitions.
	(expand_vector_operation): Drop dce_ssa_names.
	(expand_vector_operations_1): Likewise.
 2024-11-15 13:42:02 +01:00
Florian Weimer
5f71122e9d Regenerate gcc/c-family/c.opt.urls 
After commit 8833389e90.

gcc/c-family/

	* c.opt.urls: Regenerate.
 2024-11-15 13:37:54 +01:00
Pan Li
5cf7ffe047 RISC-V: Rearrange the test files for scalar SAT_SUB [NFC] 
The test files of scalar SAT_SUB only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}.  For example,
test form 3 for uint32_t SAT_SUB will have -3-u32.c for asm check and
-run-3-u32.c for the run test.

Meanwhile, all related test files moved to riscv/sat/.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_sub-2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-38.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-10-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-39.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-10-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-40.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-10-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-37.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-10-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-42.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-11-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-43.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-11-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-44.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-11-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-41.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-11-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-46.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-12-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-47.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-12-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-48.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-12-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-45.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-12-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-6.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-7.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-8.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-5.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-10.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-11.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-12.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-9.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-14.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-15.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-16.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-13.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-18.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-5-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-19.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-5-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-20.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-5-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-17.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-5-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-22.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-6-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-23.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-6-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-24.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-6-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-21.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-6-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-26.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-7-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-27.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-7-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-28.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-7-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-25.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-7-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-30.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-8-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-31.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-8-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-32.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-8-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-29.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-8-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-34.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-9-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-35.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-9-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-36.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-9-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-33.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-9-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-38.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-10-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-39.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-10-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-40.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-10-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-37.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-10-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-42.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-11-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-43.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-11-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-44.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-11-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-41.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-11-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-46.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-12-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-47.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-12-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-48.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-12-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-45.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-12-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-6.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-7.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-8.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-5.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-10.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-11.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-12.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-9.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-14.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-15.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-16.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-13.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-18.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-5-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-19.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-5-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-20.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-5-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-17.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-5-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-22.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-6-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-23.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-6-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-24.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-6-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-21.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-6-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-26.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-7-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-27.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-7-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-28.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-7-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-25.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-7-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-30.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-8-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-31.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-8-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-32.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-8-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-29.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-8-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-34.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-9-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-35.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-9-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-36.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-9-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub-run-33.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub-run-9-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-2_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-2_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-2_3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-2_4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-3_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-3_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-3_3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-3_4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-4_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-4_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-1_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-1_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-1_3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-1_4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-6_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-6_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-6_3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-6.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-15_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-15_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-7_3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-7.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-8_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-16.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-5_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-5_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-5_3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-5.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-10_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-10_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-10.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-11_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-11_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-11.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-12.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-9_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-9_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-9.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-14_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-14_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-14.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-7_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-7_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-15.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-8.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-13_1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-13_2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-13.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-2.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-3.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-4.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-1.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-6.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-7.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-8.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-5.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-10.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-11.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-12.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-9.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-14.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-15.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-16.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_sub_imm-run-13.c: Move to...
	* gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c: ...here.

Signed-off-by: Pan Li <pan2.li@intel.com>
 2024-11-15 20:31:06 +08:00
Florian Weimer
8833389e90 c: Introduce -Wmissing-parameter-name 
Empirically, omitted parameter names are difficult to catch in code
review.  With this change, projects can build with
-Werror=missing-parameter-name, to avoid this unnecessary
incompatibility with older GCC versions.  The existing
-pedantic-errors option is too broad for that because it also flags
widely used and widely available GCC extensions.  Likewise for
-Werror=c11-c23-compat.

gcc/c-family/

	* c-opts.cc (c_common_post_options): Initialize
	warn_missing_parameter_name.
	* c.opt (Wmissing-parameter-name): New.

gcc/c/
	* c-decl.cc (store_parm_decls_newstyle): Use
	OPT_Wmissing_parameter_name for missing parameter name
	warning.
	* c-errors.cc (pedwarn_c11): Enable fine-grained warning
	control via the option_id argument.

gcc/

	* doc/invoke.texi: Document Wmissing-parameter-name.

gcc/testsuite/

	* gcc.dg/Wmissing-parameter-name-1.c: New test.
	* gcc.dg/Wmissing-parameter-name-2.c: New test.
	* gcc.dg/Wmissing-parameter-name-3.c: New test.
 2024-11-15 12:18:42 +01:00
Florian Weimer
71bf2bef5e Report the section name in case of section type conflicts 
The section name might the user a hint of what is going on.

gcc/

	* varasm.cc (get_section): Include name of section in
	diagnostic messages.
 2024-11-15 12:00:47 +01:00
Pan Li
9676da9fc2 RISC-V: Remove unnecessary option for scalar SAT_ADD testcase 
After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase.  Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases.  The riscv.exp will pass sorts of different optimization
options for each case.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_s_add-1-i16.c: Remove flto
	dg-skip workaround and -O3 option.
	* gcc.target/riscv/sat/sat_s_add-1-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-1-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-1-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i16.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i16.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i16.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-1-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-2-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-2.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-3-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-3.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-4.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-1-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-1-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-1-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-1-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-2-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-2-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-2-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-2-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-3-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-3-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-3-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-3-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-4-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-4-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-4-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-4-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-5-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-5-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-5-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-5-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-6-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-6-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-6-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add-6-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-1-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-1-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-1-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-1-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-2-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-2-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-2-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-2-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-3-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-3-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-3-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-3-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-4-u16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-4-u32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-4-u64.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm-4-u8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-1.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-10.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-11.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-12.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-13.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-14.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-15.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-16.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-17.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-18.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-19.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-2.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-20.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-21.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-22.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-23.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-24.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-25.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-26.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-27.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-28.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-29.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-3.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-30.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-31.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-32.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-33.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-34.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-35.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-36.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-37.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-38.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-39.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-4.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-40.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-41.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-42.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-43.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-44.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-45.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-46.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-47.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-48.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-49.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-5.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-50.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-51.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-52.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-53.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-54.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-55.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-56.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-57.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-58.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-59.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-6.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-60.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-7.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-8.c: Ditto.
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-9.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Pan Li <pan2.li@intel.com>
 2024-11-15 18:47:49 +08:00
Jakub Jelinek
e505081980 testsuite: Change 3 tests from c++14 to c++11 
These tests are valid C++11, so we can run them in C++11 too.

2024-11-15  Jakub Jelinek  <jakub@redhat.com>

	* g++.dg/tree-ssa/pr116868.C: Change effective target from c++14 to
	c++11.
	* g++.dg/tree-ssa/pr96945.C: Likewise.
	* g++.dg/tree-ssa/pr110819.C: Likewise.
 2024-11-15 09:05:25 +01:00
Jakub Jelinek
1910ecf15b c: Add _Decimal64x support 
The following patch adds _Decimal64x type support.  Our dfp libraries (dpd &
libbid) can only handle decimal32, decimal64 and decimal128 formats and I
don't see that changing any time soon, so the following patch just hardcodes
that _Decimal64x has the same mode as _Decimal128 (but is a distinct type).
In the unlikely event some target would introduce something different that
can be of course changed with target hooks but would be an ABI change.
_Decimal128x is optional and we don't have a wider decimal type, so that
type isn't added.

2024-11-15  Jakub Jelinek  <jakub@redhat.com>

gcc/
	* tree-core.h (enum tree_index): Add TI_DFLOAT64X_TYPE.
	* tree.h (dfloat64x_type_node): Define.
	* tree.cc (build_common_tree_nodes): Initialize dfloat64x_type_node.
	* builtin-types.def (BT_DFLOAT64X): New DEF_PRIMITIVE_TYPE.
	(BT_FN_DFLOAT64X): New DEF_FUNCTION_TYPE_0.
	(BT_FN_DFLOAT64X_CONST_STRING, BT_FN_DFLOAT64X_DFLOAT64X): New
	DEF_FUNCTION_TYPE_1.
	* builtins.def (BUILT_IN_FABSD64X, BUILT_IN_INFD64X, BUILT_IN_NAND64X,
	BUILT_IN_NANSD64X): New builtins.
	* builtins.cc (expand_builtin): Handle BUILT_IN_FABSD64X.
	(fold_builtin_0): Handle BUILT_IN_INFD64X.
	(fold_builtin_1): Handle BUILT_IN_FABSD64X.
	* fold-const-call.cc (fold_const_call): Handle CFN_BUILT_IN_NAND64X
	and CFN_BUILT_IN_NANSD64X.
	* ginclude/float.h (DEC64X_MANT_DIG, DEC64X_MIN_EXP, DEC64X_MAX_EXP,
	DEC64X_MAX, DEC64X_EPSILON, DEC64X_MIN, DEC64X_TRUE_MIN,
	DEC64X_SNAN): Redefine.
gcc/c-family/
	* c-common.h (enum rid): Add RID_DFLOAT64X.
	* c-common.cc (c_global_trees): Fix comment typo.  Add
	dfloat64x_type_node.
	(c_common_nodes_and_builtins): Handle RID_DFLOAT64X.
	* c-cppbuiltin.cc (c_cpp_builtins): Call
	builtin_define_decimal_float_constants also for dfloat64x_type_node
	if non-NULL.
	* c-lex.cc (interpret_float): Handle d64x suffixes.
	* c-pretty-print.cc (pp_c_floating_constant): Print d64x suffixes
	on dfloat64x_type_node typed constants.
gcc/c/
	* c-tree.h (enum c_typespec_keyword): Add cts_dfloat64x and adjust
	comment.
	* c-parser.cc (c_keyword_starts_typename, c_token_starts_declspecs,
	c_parser_declspecs, c_parser_gnu_attribute_any_word): Handle
	RID_DFLOAT64X.
	(c_parser_postfix_expression): Handle _Decimal64x arguments in
	__builtin_tgmath.
	(warn_for_abs): Handle BUILT_IN_FABSD64X.
	* c-decl.cc (declspecs_add_type): Handle cts_dfloat64x and
	RID_DFLOAT64X.
	(finish_declspecs): Handle cts_dfloat64x.
	* c-typeck.cc (c_common_type): Handle dfloat64x_type_node.
gcc/testsuite/
	* gcc.dg/dfp/c11-decimal64x-1.c: New test.
	* gcc.dg/dfp/c11-decimal64x-2.c: New test.
	* gcc.dg/dfp/c23-decimal64x-1.c: New test.
	* gcc.dg/dfp/c23-decimal64x-2.c: New test.
	* gcc.dg/dfp/c23-decimal64x-3.c: New test.
	* gcc.dg/dfp/c23-decimal64x-4.c: New test.
libcpp/
	* expr.cc (interpret_float_suffix): Handle d64x and D64x
	suffixes, adjust comment.
 2024-11-15 08:43:48 +01:00
Marek Polacek
3757009af7 testsuite: fix g++.dg/tree-ssa/pr58483.C 
This test mistakenly used two dg-do compile.  Since it passes
in C++11 as well, we can run it in C++11 and up.

gcc/testsuite/ChangeLog:

	* g++.dg/tree-ssa/pr58483.C: Run in C++11 and up.
 2024-11-15 00:02:44 -05:00
Pan Li
e0a402b3e2 RISC-V: Move scalar SAT_ADD test cases to a isolated folder 
Move the scalar SAT_ADD includes both the signed and unsigned
integer to the folder gcc.target/riscv/sat.  According to the
implementation the below options will be appended for each
test cases.

* -O2
* -O3
* -Ofast
* -Os
* -Oz

Then we can see the test log similar as below:

Executing on host: .../sat_s_add-1-i8.c ...  -O2 -march=rv64gc -S -o sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -O3 -march=rv64gc -S -o sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -Ofast -march=rv64gc -S -o sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -Oz -march=rv64gc -S -o sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -Os -march=rv64gc -S -o sat_s_add-1-i8.s

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

Committed as pre-approved by kito.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/riscv.exp: Add new folder sat under riscv
	and add 5 options for each sat test.
	* gcc.target/riscv/sat_s_add-1-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-1-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-1-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-1-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-1-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-1-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-1-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-1-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-2-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-2-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-2-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-2-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-2-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-2-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-2-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-2-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-3-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-3-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-3-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-3-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-3-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-3-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-3-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-3-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-4-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-4-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-4-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-4-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-4-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-4-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-4-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-4-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-run-1-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-1-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-run-1-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-1-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-run-1-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-1-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-run-1-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-1-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-run-2-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-2-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-run-2-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-2-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-run-2-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-2-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-run-2-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-2-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-run-3-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-3-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-run-3-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-3-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-run-3-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-3-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-run-3-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-3-i8.c: ...here.
	* gcc.target/riscv/sat_s_add-run-4-i16.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-4-i16.c: ...here.
	* gcc.target/riscv/sat_s_add-run-4-i32.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-4-i32.c: ...here.
	* gcc.target/riscv/sat_s_add-run-4-i64.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-4-i64.c: ...here.
	* gcc.target/riscv/sat_s_add-run-4-i8.c: Move to...
	* gcc.target/riscv/sat/sat_s_add-run-4-i8.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-1-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-1.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-2-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-2-1.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-2.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-2.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-3-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-3-1.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-3.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-3.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-4.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-4.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-run-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-run-2.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-2.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-run-3.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-3.c: ...here.
	* gcc.target/riscv/sat_s_add_imm-run-4.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-4.c: ...here.
	* gcc.target/riscv/sat_u_add-1-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-1-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-1-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-1-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-2-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-2-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-2-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-2-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-3-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-3-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-3-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-3-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-4-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-4-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-4-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-4-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-5-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-5-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-5-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-5-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-5-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-5-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-5-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-5-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-6-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-6-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-6-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-6-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-6-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-6-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-6-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-6-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-run-1-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-run-1-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-run-1-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-run-1-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-run-2-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-run-2-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-run-2-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-run-2-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-run-3-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-run-3-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-run-3-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-run-3-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-run-4-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-run-4-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-run-4-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-run-4-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-run-5-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-5-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-run-5-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-5-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-run-5-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-5-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-run-5-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-5-u8.c: ...here.
	* gcc.target/riscv/sat_u_add-run-6-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-6-u16.c: ...here.
	* gcc.target/riscv/sat_u_add-run-6-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-6-u32.c: ...here.
	* gcc.target/riscv/sat_u_add-run-6-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-6-u64.c: ...here.
	* gcc.target/riscv/sat_u_add-run-6-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add-run-6-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-1-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-1-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-1-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-1-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-2-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-2-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-2-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-2-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-3-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-3-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-3-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-3-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-4-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-4-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-4-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-4-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-1-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-1-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-1-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-1-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-2-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-2-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-2-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-2-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-3-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-3-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-3-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-3-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-4-u16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-4-u32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-4-u64.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c: ...here.
	* gcc.target/riscv/sat_u_add_imm-run-4-u8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-1.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-1.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-10.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-10.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-11.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-11.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-12.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-12.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-13.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-13.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-14.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-14.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-15.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-15.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-16.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-16.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-17.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-17.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-18.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-18.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-19.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-19.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-2.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-2.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-20.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-20.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-21.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-21.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-22.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-22.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-23.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-23.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-24.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-24.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-25.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-25.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-26.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-26.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-27.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-27.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-28.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-28.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-29.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-29.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-3.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-3.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-30.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-30.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-31.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-31.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-32.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-32.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-33.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-33.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-34.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-34.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-35.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-35.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-36.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-36.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-37.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-37.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-38.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-38.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-39.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-39.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-4.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-4.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-40.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-40.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-41.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-41.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-42.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-42.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-43.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-43.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-44.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-44.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-45.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-45.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-46.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-46.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-47.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-47.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-48.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-48.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-49.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-49.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-5.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-5.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-50.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-50.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-51.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-51.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-52.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-52.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-53.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-53.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-54.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-54.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-55.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-55.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-56.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-56.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-57.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-57.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-58.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-58.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-59.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-59.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-6.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-6.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-60.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-60.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-7.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-7.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-8.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-8.c: ...here.
	* gcc.target/riscv/sat_u_add_imm_type_check-9.c: Move to...
	* gcc.target/riscv/sat/sat_u_add_imm_type_check-9.c: ...here.
	* gcc.target/riscv/sat/sat_arith.h: New test.
	* gcc.target/riscv/sat/sat_arith_data.h: New test.
	* gcc.target/riscv/sat/scalar_sat_binary.h: New test.
	* gcc.target/riscv/sat/scalar_sat_binary_run_xxx.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
 2024-11-15 12:57:03 +08:00
Kewen Lin
96a468842e rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p5 
The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 5, it's to refactor all the handlings of vector
integer comparison to make it neat.  This patch doesn't
introduce any functionality change.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refactor the
	handlings of vector integer comparison.
 2024-11-15 03:46:33 +00:00
Kewen Lin
c8e5c0e01e rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p4 
The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 4, it's to rework the handlings on GE/GEU/LE/LEU,
also make the function not recursive any more.  This patch
doesn't introduce any functionality change.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refine the
	handlings for operators GE/GEU/LE/LEU.
 2024-11-15 03:46:33 +00:00
Kewen Lin
35c83e66c0 rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p3 
The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 3, it's to refactor the handlings on NE.
This patch doesn't introduce any functionality change.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refactor the
	handlings for operator NE.
 2024-11-15 03:46:33 +00:00
Kewen Lin
d35ee820b4 rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p2 
The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 2, it's to refactor the handlings on LT and LTU.
This patch doesn't introduce any functionality change.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refine the
	handlings for operators LT and LTU.
 2024-11-15 03:46:33 +00:00
Kewen Lin
311bcf9d4c rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p1 
The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 1, it's to remove the helper function
rs6000_emit_vector_compare_inner and move the logics into
rs6000_emit_vector_compare.  This patch doesn't introduce any
functionality change.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Remove.
	(rs6000_emit_vector_compare): Emit rtx comparison for operators EQ/
	GT/GTU directly.
 2024-11-15 03:46:33 +00:00
Kewen Lin
2e22882f3e rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p4 
All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 4, it further checks for comparison opeators
LT/UNGE.  In rs6000_emit_vector_compare, for the handling
of LT, it switches to use code GT, swaps operands and try
again, it's exactly the same as what we have in vector.md:

; lt(a,b)   = gt(b,a)

As to UNGE, in rs6000_emit_vector_compare, it uses reversed
code LT and further operates on the result with one_cmpl,
it's also the same as what's in vector.md:

; unge(a,b) = ~lt(a,b)

This patch should not have any functionality change too.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Emit rtx
	comparison for operators LT/UNGE of MODE_VECTOR_FLOAT directly.
	(rs6000_emit_vector_compare): Move assertion of no MODE_VECTOR_FLOAT to
	function beginning.
 2024-11-15 03:46:33 +00:00
Kewen Lin
893ee27356 rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p3 
All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 3, it further checks for comparison opeators
LE/UNGT.  In rs6000_emit_vector_compare, UNGT is handled
with reversed code LE and inverting with one_cmpl_optab,
LE is handled with LT ior EQ, while in vector.md, we have
the support:

; le(a,b)   = ge(b,a)
; ungt(a,b) = ~le(a,b)

The associated test case shows it's an improvement.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
	comparison for operators LE/UNGT of MODE_VECTOR_FLOAT directly.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/vcond-fp.c: New test.
 2024-11-15 03:46:32 +00:00
Kewen Lin
5210565ec1 rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p2 
All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 2, it further checks for comparison opeators
NE/UNLE/UNLT.  In rs6000_emit_vector_compare, they are
handled with reversed code which is queried from function
reverse_condition_maybe_unordered and inverting with
one_cmpl_optab.  It's the same as what we have in vector.md:

; ne(a,b)   = ~eq(a,b)
; unle(a,b) = ~gt(a,b)
; unlt(a,b) = ~ge(a,b)

The operators on the right side have been supported in part 1.
This patch should not have any functionality change too.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
	comparison for operators NE/UNLE/UNLT of MODE_VECTOR_FLOAT directly.
 2024-11-15 03:46:32 +00:00
Kewen Lin
a2da2fca00 rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p1 
All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 1, it only handles the operators which are
already emitted with an rtx comparison previously in function
rs6000_emit_vector_compare_inner, they are EQ/GT/GE/ORDERED/
UNORDERED/UNEQ/LTGT.  There is no functionality change.

With this change, rs6000_emit_vector_compare_inner would
only work for vector integer comparison handling, it would
be cleaned up later in vector integer comparison rework.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Move
	MODE_VECTOR_FLOAT handlings out.
	(rs6000_emit_vector_compare): Emit rtx comparison for operators EQ/GT/
	GE/UNORDERED/ORDERED/UNEQ/LTGT of MODE_VECTOR_FLOAT directly, and
	adjust one call site of rs6000_emit_vector_compare_inner to
	rs6000_emit_vector_compare.
 2024-11-15 03:46:32 +00:00
GCC Administrator
715eb6610b Daily bump. 2024-11-15 00:16:23 +00:00
Jonathan Wakely
71f221a8be
libstdc++: Fix indentation in std::list::emplace_back 
libstdc++-v3/ChangeLog:

	* include/bits/stl_list.h (list::emplace_back): Fix indentation.
 2024-11-15 00:01:51 +00:00
Jeff Law
aaada43a2a [RISC-V][V2] Fix type on vector move patterns 
Updated version of my prior patch to fix type attributes on the
pre-allocation vector move pattern.  This version just adds a suitable
set of attributes to a second pattern that was obviously wrong.

Passed on my tester for rv64 and rv32 crosses.  Bootstrapped and
regression tested on riscv64-linux-gnu as well.

--

So I was looking into a horrific schedule for SAD a week or so ago and
came across this gem.

Basically we were treating a vector load as a vector move from a
scheduling standpoint during sched1.  Naturally we didn't expose much
ILP during sched1.  That in turn caused the register allocator to pack
the pseudos onto the physical vector registers tightly.  regrename
didn't do anything useful and the resulting code had too many false
dependencies for sched2 to do anything useful.

As a result we were taking many load->use stalls in x264's SAD routine.

I'm confident the types are fine, but I'm a lot less sure about the
other attributes (mode, avl_type_index, mode_idx).  If someone could
take a look at that, it'd be greatly appreciated.

There's other cases that may need similar treatment.  But I didn't want
to muck with them until I understood those other attributes and how they
need adjustments.

In particular mov<VLS_AVL_REG:mode><P:mode>_lra appears to have the same
problem.

--

gcc/
	* config/riscv/vector.md (mov<mode> pattern/splitter): Fix type and
	other attributes.
	(mov<VLS_AVL_REG:mode><P:mode>_lra): Likewise.
 2024-11-14 16:58:53 -07:00
Harald Anlauf
f70c1d517e Fortran: fix passing of NULL() actual argument to character dummy [PR104819] 
Ensure that character length is set and passed by the call to a procedure
when its dummy argument is NULL() with MOLD argument present, or set length
to either 0 or the callee's expected character length.  For assumed-rank
dummies, use the rank of the MOLD argument.  Generate temporaries for
passed arguments when needed.

	PR fortran/104819

gcc/fortran/ChangeLog:

	* trans-expr.cc (conv_null_actual): Helper function to handle
	passing of NULL() to non-optional dummy arguments of non-bind(c)
	procedures.
	(gfc_conv_procedure_call): Use it for character dummies.

gcc/testsuite/ChangeLog:

	* gfortran.dg/null_actual_6.f90: New test.
 2024-11-14 22:37:56 +01:00
Sam James
7744da67e9
gcc: regenerate configure 
r15-5257-g56ded80b96b0f6 didn't regenerate configure correctly.

See https://inbox.sourceware.org/gcc-patches/ZzZf69gORVPRo6Ct@zen.kayari.org/.

gcc/ChangeLog:

	* configure: Regenerate.
 2024-11-14 20:53:26 +00:00
Denis Chertykov
fe1486e118 The fix for PR117191 
Wrong code appears after dse2 pass because it removes necessary insns.
(ie insn 554 - store to frame spill slot)
This happened because LRA pass doesn't cleanup the code exactly like reload does.
The reload1.c has a special pass for such cleanup.
The reload removes CLOBBER insns with spill slots like this:
(insn 202 184 186 7 (clobber (mem/c:TI (plus:HI (reg/f:HI 28 r28)
                (const_int 1 [0x1])) [3 %sfp+1 S16 A8])) -1
     (nil))

Fragment from reload1.c:
--------------------------------------------------------------------------------
  reload_completed = 1;

  /* Make a pass over all the insns and delete all USEs which we inserted
     only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
     notes.  Delete all CLOBBER insns, except those that refer to the return
     value and the special mem:BLK CLOBBERs added to prevent the scheduler
     from misarranging variable-array code, and simplify (subreg (reg))
     operands.  Strip and regenerate REG_INC notes that may have been moved
     around.  */

  for (insn = first; insn; insn = NEXT_INSN (insn))
    if (INSN_P (insn))
      {
	rtx *pnote;

	if (CALL_P (insn))
	  replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
			      VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));

	if ((GET_CODE (PATTERN (insn)) == USE
	     /* We mark with QImode USEs introduced by reload itself.  */
	     && (GET_MODE (insn) == QImode
		 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
	    || (GET_CODE (PATTERN (insn)) == CLOBBER
		&& (!MEM_P (XEXP (PATTERN (insn), 0))
		    || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
		    || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
			&& XEXP (XEXP (PATTERN (insn), 0), 0)
				!= stack_pointer_rtx))
		&& (!REG_P (XEXP (PATTERN (insn), 0))
		    || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
	  {
	    delete_insn (insn);
	    continue;
	  }
--------------------------------------------------------------------------------

LRA have a similar place where it removes unnecessary insns, but not CLOBBER insns with
memory spill slots. It's `lra_final_code_change' function.

I just mark a CLOBBER insn with pseudo spilled to memory for removing it later together
with LRA temporary CLOBBER insns.

	PR rtl-optimization/117191
gcc/
	* lra-spills.cc (spill_pseudos): Mark a CLOBBER insn with pseudo
	spilled to memory for removing it later together with LRA temporary
	CLOBBER insns.
 2024-11-15 00:50:36 +04:00
Jonathan Wakely
45cc42d6dc
libstdc++: Make equal and is_permutation short-circuit (LWG 3560) 
We already implement short-circuiting for random access iterators, but
we also need to do so for ranges::equal and ranges::is_permutation when
given sized ranges that are not random access ranges (e.g. std::list).

libstdc++-v3/ChangeLog:

	* include/bits/ranges_algo.h (__is_permutation_fn::operator()):
	Short-circuit for sized ranges with different sizes, as per LWG
	3560.
	* include/bits/ranges_algobase.h (__equal_fn::operator()):
	Likewise.
	* include/bits/stl_algo.h (__is_permutation): Use if-constexpr
	for random access iterator branches.
	* include/bits/stl_algobase.h (__equal4): Likewise.
	* testsuite/25_algorithms/equal/lwg3560.cc: New test.
	* testsuite/25_algorithms/is_permutation/lwg3560.cc: New test.

Reviewed-by: Patrick Palka <ppalka@redhat.com>
 2024-11-14 20:01:25 +00:00
Martin Jambor
012f5a22ba
ipa: Rationalize IPA-VR computations across pass-through jump functions 
Currently ipa_value_range_from_jfunc and
propagate_vr_across_jump_function contain similar but not same code
for dealing with pass-through jump functions.  This patch puts these
common bits into one function which can also handle comparison
operations.

gcc/ChangeLog:

2024-11-01  Martin Jambor  <mjambor@suse.cz>

	PR ipa/114985
	* ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): New function.
	(ipa_value_range_from_jfunc): Move the common functionality to the
	above new function, adjust the rest so that it works with it well.
	(propagate_vr_across_jump_function): Likewise.
 2024-11-14 20:55:22 +01:00
Patrick Palka
361050589b libstdc++: Implement LWG 3563 changes to keys_view and values_view 
This LWG issue corrects the definition of these alias templates to make
them suitable for alias CTAD.

libstdc++-v3/ChangeLog:

	* include/std/ranges (keys_view): Adjust as per LWG 3563.
	(values_view): Likewise.
	* testsuite/std/ranges/adaptors/elements.cc (test08): New test.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
 2024-11-14 13:27:41 -05:00
Jonathan Wakely
4a3a0be34f
libstdc++: Fix get<0> constraint for lvalue ranges::subrange (LWG 3589) 
Apprived at October 2021 plenary.

libstdc++-v3/ChangeLog:

	* include/bits/ranges_util.h (subrange::begin): Fix constraint,
	as per LWG 3589.
	* testsuite/std/ranges/subrange/lwg3589.cc: New test.
 2024-11-14 17:34:29 +00:00
GCC Administrator
5673fc0c7b Daily bump. 2024-11-14 17:20:15 +00:00
Jeff Law
e5d6e857af contrib: Add another ignored commit 
* gcc-changelog/git_update_version.py (ignored_commits): Add
	another ignored commit.
 2024-11-14 10:14:53 -07:00
Jonathan Wakely
e627a941dc
libstdc++: Make _GLIBCXX_NODISCARD work for C++11 and C++14 
The _GLIBCXX_NODISCARD macro only expands to [[__nodiscard__]] for C++17
and later, but all supported compilers will allow us to use that for
C++11 and C++14 too. Enable it for those older standards, to give
improved diagnostics for users of those older standards.

libstdc++-v3/ChangeLog:

	* include/bits/c++config (_GLIBCXX_NODISCARD): Expand for C++11
	and C++14.
	* testsuite/22_locale/locale/cons/12438.cc: Adjust dg-warning to
	expect nodiscard warnings for C++11 and C++14 as well.
	* testsuite/22_locale/locale/operations/2.cc: Likewise.
	* testsuite/25_algorithms/equal/debug/1_neg.cc: Likewise.
	* testsuite/25_algorithms/equal/debug/2_neg.cc: Likewise.
	* testsuite/25_algorithms/equal/debug/3_neg.cc: Likewise.
	* testsuite/25_algorithms/find_first_of/concept_check_1.cc:
	Likewise.
	* testsuite/25_algorithms/is_permutation/2.cc: Likewise.
	* testsuite/25_algorithms/lexicographical_compare/71545.cc:
	Likewise.
	* testsuite/25_algorithms/lower_bound/33613.cc: Likewise.
	* testsuite/25_algorithms/lower_bound/debug/irreflexive.cc:
	Likewise.
	* testsuite/25_algorithms/lower_bound/debug/partitioned_neg.cc:
	Likewise.
	* testsuite/25_algorithms/lower_bound/debug/partitioned_pred_neg.cc: Likewise.
	* testsuite/25_algorithms/minmax/3.cc: Likewise.
	* testsuite/25_algorithms/search/78346.cc: Likewise.
	* testsuite/25_algorithms/search_n/58358.cc: Likewise.
	* testsuite/25_algorithms/unique/1.cc: Likewise.
	* testsuite/25_algorithms/unique/11480.cc: Likewise.
	* testsuite/25_algorithms/upper_bound/33613.cc: Likewise.
	* testsuite/25_algorithms/upper_bound/debug/partitioned_neg.cc:
	Likewise.
	* testsuite/25_algorithms/upper_bound/debug/partitioned_pred_neg.cc: Likewise.
	* testsuite/27_io/ios_base/types/fmtflags/bitmask_operators.cc:
	Likewise.
	* testsuite/27_io/ios_base/types/iostate/bitmask_operators.cc:
	Likewise.
	* testsuite/27_io/ios_base/types/openmode/bitmask_operators.cc:
	Likewise.
	* testsuite/ext/concept_checks.cc: Likewise.
	* testsuite/ext/is_heap/47709.cc: Likewise.
	* testsuite/ext/is_sorted/cxx0x.cc: Likewise.
 2024-11-14 17:00:40 +00:00
Jeff Law
c924a03ae1 contrib: Add 2 further ignored commits 
I goof'd and double-reverted a change.  Add those to the ignore
list, leaving the final reversion as-is.

	* gcc-changelog/git_update_version.py (ignored_commits): Add 2
	further commits.
 2024-11-14 09:44:54 -07:00
Jason Merrill
985bc95bd6 libstdc++: stdc++.h and <coroutine> 
r13-3036 moved #include <coroutine> into the new freestanding section, but
also moved it from a C++20 section to a C++23 section.  This patch moves it
back.

Incidentally, I'm curious why a few headers were removed from the hosted
section (including <coroutine>), but most were left in place, so we have
redundant includes of most hosted headers.

libstdc++-v3/ChangeLog:

	* include/precompiled/stdc++.h: <coroutine> is C++20.
 2024-11-14 11:39:31 -05:00
Jason Merrill
835530f4ee c++: fix namespace alias export 
This affected std::views in module std.

gcc/cp/ChangeLog:

	* name-lookup.cc (do_namespace_alias): set_originating_module after
	pushdecl.

gcc/testsuite/ChangeLog:

	* g++.dg/modules/namespace-7_a.C: New test.
	* g++.dg/modules/namespace-7_b.C: New test.
 2024-11-14 11:34:06 -05:00
Jason Merrill
e8ebc91615 c++: module dialect tweak 
Coroutines have been enabled by -std=c++20 since GCC 11.

gcc/cp/ChangeLog:

	* module.cc (module_state_config::get_dialect): Expect coroutines in
	C++20.
 2024-11-14 11:34:06 -05:00
Jan Hubicka
2361049082 Fix common.opt.urls 
gcc/ChangeLog:

	* common.opt.urls: Fix.
 2024-11-14 17:29:14 +01:00
Jeff Law
72677e1119 Revert "Reapply "[PATCH v2] RISC-V: zero_extend(not) -> xor optimization [PR112398]"" 
This reverts commit 10d76b7f1e.
 2024-11-14 09:26:11 -07:00
Yury Khrustalev
4bce1f71c9 aarch64: Fix nonlocal goto tests incompatible with GCS 
gcc/testsuite/ChangeLog:
	* gcc.target/aarch64/gcs-nonlocal-3.c: New test.
	* gcc.target/aarch64/sme/nonlocal_goto_4.c: Update.
	* gcc.target/aarch64/sme/nonlocal_goto_5.c: Update.
	* gcc.target/aarch64/sme/nonlocal_goto_6.c: Update.
 2024-11-14 16:15:14 +00:00
Matthieu Longo
6cc6f75374 aarch64: Fix tests incompatible with GCS 
gcc/testsuite/ChangeLog:

	* g++.target/aarch64/return_address_sign_ab_exception.C: Update.
	* gcc.target/aarch64/eh_return.c: Update.
 2024-11-14 16:15:14 +00:00
Richard Ball
e36249f822 aarch64: Add tests and docs for indirect_return attribute 
This patch adds a new testcase and docs for indirect_return
attribute.

gcc/ChangeLog:

	* doc/extend.texi: Add AArch64 docs for indirect_return
	attribute.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/indirect_return-1.c: New test.
	* gcc.target/aarch64/indirect_return-2.c: New test.
	* gcc.target/aarch64/indirect_return-3.c: New test.

Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
 2024-11-14 16:15:13 +00:00
Szabolcs Nagy
80fabc8d6b aarch64: Introduce indirect_return attribute 
Tail calls of indirect_return functions from non-indirect_return
functions are disallowed even if BTI is disabled, since the call
site may have BTI enabled.

Needed for swapcontext within the same function when GCS is enabled.

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_gnu_attributes): Add
	indirect_return.
	(aarch64_gen_callee_cookie): Use indirect_return attribute.
	(aarch64_callee_indirect_return): New.
	(aarch_fun_is_indirect_return): New.
	(aarch64_function_ok_for_sibcall): Disallow tail calls if caller
	is non-indirect_return but callee is indirect_return.
	(aarch64_function_arg): Add indirect_return to cookie.
	(aarch64_init_cumulative_args): Record indirect_return in
	CUMULATIVE_ARGS.
	(aarch64_comp_type_attributes): Check indirect_return attribute.
	(aarch64_output_mi_thunk): Add indirect_return to cookie.
	* config/aarch64/aarch64.h (CUMULATIVE_ARGS): Add new field
	indirect_return.
	* config/aarch64/aarch64.md (tlsdesc_small_<mode>): Update.
	* config/aarch64/aarch64-opts.h (AARCH64_NUM_ABI_ATTRIBUTES): New.
	* config/aarch64/aarch64-protos.h (aarch64_gen_callee_cookie): Update.
	* config/arm/aarch-bti-insert.cc (call_needs_bti_j): New.
	(rest_of_insert_bti): Use call_needs_bti_j.
	* config/arm/aarch-common-protos.h
	(aarch_fun_is_indirect_return): New.
	* config/arm/arm.cc
	(aarch_fun_is_indirect_return): New.

Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
 2024-11-14 16:15:13 +00:00
Szabolcs Nagy
6f73c29d2f aarch64: libatomic: add GCS marking to asm 
libatomic/ChangeLog:

	* config/linux/aarch64/atomic_16.S (FEATURE_1_GCS): Define.
	(GCS_FLAG): Define if GCS is enabled.
	(GNU_PROPERTY): Add GCS_FLAG.
 2024-11-14 16:15:12 +00:00
Szabolcs Nagy
d8374290e5 aarch64: libgcc: add GCS marking to asm 
libgcc/ChangeLog:

	* config/aarch64/aarch64-asm.h (FEATURE_1_GCS): Define.
	(GCS_FLAG): Define if GCS is enabled.
	(GNU_PROPERTY): Add GCS_FLAG.
 2024-11-14 16:15:12 +00:00
Szabolcs Nagy
608da24401 aarch64: Emit GNU property NOTE for GCS 
gcc/ChangeLog:

	* config/aarch64/aarch64.cc (GNU_PROPERTY_AARCH64_FEATURE_1_GCS):
	Define.
	(aarch64_file_end_indicate_exec_stack): Set GCS property bit.
 2024-11-14 16:15:11 +00:00
Szabolcs Nagy
2a330ec149 aarch64: Add GCS support to the unwinder 
Follows the current linux ABI that uses single signal entry token
and shared shadow stack between thread and alt stack.
Could be behind __ARM_FEATURE_GCS_DEFAULT ifdef (only do anything
special with gcs compat codegen) but there is a runtime check anyway.

Change affected tests to be compatible with -mbranch-protection=standard

libgcc/ChangeLog:

	* config/aarch64/aarch64-unwind.h (_Unwind_Frames_Extra): Update.
	(_Unwind_Frames_Increment): Define.
 2024-11-14 16:15:11 +00:00
Szabolcs Nagy
c283cf27b0 aarch64: Add target pragma tests for gcs 
gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add gcs specific
	tests.
 2024-11-14 16:15:10 +00:00
Szabolcs Nagy
500de6c0e5 aarch64: Add test for GCS ACLE defs 
gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/pragma_cpp_predefs_1.c: GCS test.
 2024-11-14 16:15:10 +00:00