Linus Torvalds de0a9f4486 RISC-V Fixes for 6.10-rc6 ... * A fix for vector load/store instruction decoding, which could result in reserved vector element length encodings decoding as valid vector instructions. * Instruction patching now aggressively flushes the local instruction cache, to avoid situations where patching functions on the flush path results in torn instructions being fetched. * A fix to prevent the stack walker from showing up as part of traces. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmZ+4zUTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiTXxD/wPSWbHf24Mr4CrFYbKR7lHWjGku+jG 8LQa+B9uUgpA8XjNjeeECg7lsJq/1avbPrUlValRckUIMZPHSWK4U7aFkkPs1WFa 87D5pA4AVkt5U8v/3c5GQ8Tod0Afa7OyFggxdglC3XFvUa5TNdn3pdv0rdE4Mx5l QRijFyLlhRv/D5We+exNAVJmkdHfSXQEEyEjXeb83VK+PsZzAXvHLj3omxCyQ1kH Kt2RyN8QpkUisFNTpSvPHiuoPjUeJvRs0JIyrO1SwBGHyYs4kg6g0KBk4YjTTXG5 xbRVG2tMO9TS2jRRHJS7fdI+yF0X1z+t+WUG1F1WHvKxnqbWczJ0UczFgacaVSkw BM/yO+VPg22f6bM4H85K5GBdhN8PplFDuHDdVQ8/LDGOrQKaByrorXWq3WrbwJcq vVwbnBGW6v4we5COzyHvwnakzl4bEMHoUb2NVTzZM+fFleiEdx4Sg+F5Us8+UlZh PztwjPao8spIm81l/wXStxYzschDyonCt74/odic2LDtFBirZWzDdUInXFVzUZs7 CUxF38XJ6SNQJBVVwQv6qisoWhy6Ca9SGKwY2GwW7Ustx3C4Eh0nrOVmI/DcHRgN 9rGm13Qfm8eUSznTM+buWTTluZvtmZupGpAP2GhvaUgTMDIfK/vttidW9Kf4KsP8 hn+jllIc1WgE6Q== =0bpZ -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - A fix for vector load/store instruction decoding, which could result in reserved vector element length encodings decoding as valid vector instructions. - Instruction patching now aggressively flushes the local instruction cache, to avoid situations where patching functions on the flush path results in torn instructions being fetched. - A fix to prevent the stack walker from showing up as part of traces. * tag 'riscv-for-linus-6.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: stacktrace: convert arch_stack_walk() to noinstr riscv: patch: Flush the icache right after patching to avoid illegal insns RISC-V: fix vector insn load/store width mask		2024-06-28 16:14:59 -07:00
..
boot	riscv: dts: sophgo: disable write-protection for milkv duo	2024-06-19 08:46:03 +08:00
configs	RISC-V Patches for the 6.10 Merge Window, Part 1	2024-05-22 09:56:00 -07:00
crypto	crypto: riscv - add vector crypto accelerated AES-CBC-CTS	2024-03-20 08:56:11 -07:00
errata	RISC-V Patches for the 6.10 Merge Window, Part 1	2024-05-22 09:56:00 -07:00
include	RISC-V: fix vector insn load/store width mask	2024-06-25 08:47:10 -07:00
kernel	RISC-V Fixes for 6.10-rc6	2024-06-28 16:14:59 -07:00
kvm	RISC-V: KVM: Fix incorrect reg_subtype labels in kvm_riscv_vcpu_set_reg_isa_ext function	2024-05-31 10:40:39 +05:30
lib	riscv: uaccess: Relax the threshold for fast path	2024-05-22 16:12:55 -07:00
mm	Revert "riscv: mm: accelerate pagefault when badaccess"	2024-06-03 07:41:13 -07:00
net	Modules changes for v6.10-rc1	2024-05-15 14:05:08 -07:00
purgatory	Makefile: remove redundant tool coverage variables	2024-05-14 23:35:48 +09:00
tools
Kbuild
Kconfig	riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel	2024-05-30 09:42:52 -07:00
Kconfig.debug
Kconfig.errata	riscv: thead: Rename T-Head PBMT to MAE	2024-04-25 10:22:33 -07:00
Kconfig.socs	RISC-V: drop SOC_VIRT for ARCH_VIRT	2024-04-10 11:37:50 +01:00
Makefile	RISC-V Patches for the 6.10 Merge Window, Part 2	2024-05-24 10:46:35 -07:00
Makefile.postlink