Christian Marangi b95b30e50a mips: bmips: setup: make CBR address configurable ... Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>		2024-06-27 10:44:32 +02:00
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bcm47xx_private.h
board.c
buttons.c	MIPS: Fix typos	2024-01-08 10:39:12 +01:00
irq.c
Kconfig
leds.c
Makefile
Platform
prom.c	mips: bmips: rework and cache CBR addr handling	2024-06-27 10:44:24 +02:00
serial.c
setup.c	mips: bmips: setup: make CBR address configurable	2024-06-27 10:44:32 +02:00
time.c
workarounds.c