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61329a1152
Add support for userspace to enable/disable the debug ports(ADB,MIPC). - ADB port: /dev/wwan0adb0 - MIPC port: /dev/wwan0mipc0 Application can use ADB (Android Debug Bridge) port to implement functions (shell, pull, push ...) by ADB protocol commands. E.g., ADB commands: - A_OPEN: OPEN(local-id, 0, "destination") - A_WRTE: WRITE(local-id, remote-id, "data") - A_OKEY: READY(local-id, remote-id, "") - A_CLSE: CLOSE(local-id, remote-id, "") Link: https://android.googlesource.com/platform/packages/modules/adb/+/refs/heads/main/README.md Application can use MIPC (Modem Information Process Center) port to debug antenna tuner or noise profiling through this MTK modem diagnostic interface. By default, debug ports are not exposed, so using the command to enable or disable debug ports. Enable debug ports: - enable: 'echo 1 > /sys/bus/pci/devices/${bdf}/t7xx_debug_ports Disable debug ports: - disable: 'echo 0 > /sys/bus/pci/devices/${bdf}/t7xx_debug_ports Signed-off-by: Jinjian Song <jinjian.song@fibocom.com> Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
141 lines
4.8 KiB
C
141 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
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* Moises Veleta <moises.veleta@intel.com>
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*/
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#ifndef __T7XX_PCI_H__
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#define __T7XX_PCI_H__
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#include <linux/completion.h>
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#include <linux/irqreturn.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "t7xx_reg.h"
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/* struct t7xx_addr_base - holds base addresses
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* @pcie_mac_ireg_base: PCIe MAC register base
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* @pcie_ext_reg_base: used to calculate base addresses for CLDMA, DPMA and MHCCIF registers
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* @pcie_dev_reg_trsl_addr: used to calculate the register base address
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* @infracfg_ao_base: base address used in CLDMA reset operations
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* @mhccif_rc_base: host view of MHCCIF rc base addr
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*/
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struct t7xx_addr_base {
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void __iomem *pcie_mac_ireg_base;
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void __iomem *pcie_ext_reg_base;
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u32 pcie_dev_reg_trsl_addr;
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void __iomem *infracfg_ao_base;
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void __iomem *mhccif_rc_base;
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};
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typedef irqreturn_t (*t7xx_intr_callback)(int irq, void *param);
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enum t7xx_mode {
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T7XX_UNKNOWN,
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T7XX_READY,
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T7XX_RESET,
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T7XX_FASTBOOT_SWITCHING,
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T7XX_FASTBOOT_DOWNLOAD,
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T7XX_FASTBOOT_DUMP,
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T7XX_MODE_LAST, /* must always be last */
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};
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/* struct t7xx_pci_dev - MTK device context structure
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* @intr_handler: array of handler function for request_threaded_irq
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* @intr_thread: array of thread_fn for request_threaded_irq
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* @callback_param: array of cookie passed back to interrupt functions
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* @pdev: PCI device
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* @base_addr: memory base addresses of HW components
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* @md: modem interface
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* @ccmni_ctlb: context structure used to control the network data path
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* @rgu_pci_irq_en: RGU callback ISR registered and active
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* @md_pm_entities: list of pm entities
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* @md_pm_entity_mtx: protects md_pm_entities list
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* @pm_sr_ack: ack from the device when went to sleep or woke up
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* @md_pm_state: state for resume/suspend
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* @md_pm_lock: protects PCIe sleep lock
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* @sleep_disable_count: PCIe L1.2 lock counter
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* @sleep_lock_acquire: indicates that sleep has been disabled
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* @mode: indicates the device mode
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*/
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struct t7xx_pci_dev {
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t7xx_intr_callback intr_handler[EXT_INT_NUM];
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t7xx_intr_callback intr_thread[EXT_INT_NUM];
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void *callback_param[EXT_INT_NUM];
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struct pci_dev *pdev;
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struct t7xx_addr_base base_addr;
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struct t7xx_modem *md;
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struct t7xx_ccmni_ctrl *ccmni_ctlb;
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bool rgu_pci_irq_en;
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struct completion init_done;
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/* Low Power Items */
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struct list_head md_pm_entities;
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struct mutex md_pm_entity_mtx; /* Protects MD PM entities list */
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struct completion pm_sr_ack;
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atomic_t md_pm_state;
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spinlock_t md_pm_lock; /* Protects PCI resource lock */
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unsigned int sleep_disable_count;
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struct completion sleep_lock_acquire;
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#ifdef CONFIG_WWAN_DEBUGFS
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struct dentry *debugfs_dir;
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#endif
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u32 mode;
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bool debug_ports_show;
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};
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enum t7xx_pm_id {
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PM_ENTITY_ID_CTRL1,
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PM_ENTITY_ID_CTRL2,
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PM_ENTITY_ID_DATA,
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PM_ENTITY_ID_INVALID
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};
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/* struct md_pm_entity - device power management entity
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* @entity: list of PM Entities
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* @suspend: callback invoked before sending D3 request to device
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* @suspend_late: callback invoked after getting D3 ACK from device
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* @resume_early: callback invoked before sending the resume request to device
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* @resume: callback invoked after getting resume ACK from device
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* @id: unique PM entity identifier
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* @entity_param: parameter passed to the registered callbacks
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*
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* This structure is used to indicate PM operations required by internal
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* HW modules such as CLDMA and DPMA.
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*/
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struct md_pm_entity {
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struct list_head entity;
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int (*suspend)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
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void (*suspend_late)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
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void (*resume_early)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
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int (*resume)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
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enum t7xx_pm_id id;
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void *entity_param;
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};
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void t7xx_pci_disable_sleep(struct t7xx_pci_dev *t7xx_dev);
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void t7xx_pci_enable_sleep(struct t7xx_pci_dev *t7xx_dev);
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int t7xx_pci_sleep_disable_complete(struct t7xx_pci_dev *t7xx_dev);
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int t7xx_pci_pm_entity_register(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity);
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int t7xx_pci_pm_entity_unregister(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity);
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void t7xx_pci_pm_init_late(struct t7xx_pci_dev *t7xx_dev);
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void t7xx_pci_pm_exp_detected(struct t7xx_pci_dev *t7xx_dev);
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void t7xx_mode_update(struct t7xx_pci_dev *t7xx_dev, enum t7xx_mode mode);
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int t7xx_pci_reprobe(struct t7xx_pci_dev *t7xx_dev, bool boot);
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int t7xx_pci_reprobe_early(struct t7xx_pci_dev *t7xx_dev);
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#endif /* __T7XX_PCI_H__ */
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