mirror of
https://github.com/torvalds/linux.git
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7d5a7dd5a3
Some of the registers are aligned on a 32bit boundary, causing
alignment faults on 64bit platforms.
Unable to handle kernel paging request at virtual address ffffffc084a1d004
Mem abort info:
ESR = 0x0000000096000061
EC = 0x25: DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
FSC = 0x21: alignment fault
Data abort info:
ISV = 0, ISS = 0x00000061, ISS2 = 0x00000000
CM = 0, WnR = 1, TnD = 0, TagAccess = 0
GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
swapper pgtable: 4k pages, 39-bit VAs, pgdp=0000000046ad6000
[ffffffc084a1d004] pgd=100000013ffff003, p4d=100000013ffff003, pud=100000013ffff003, pmd=0068000020a00711
Internal error: Oops: 0000000096000061 [#1] SMP
Modules linked in: mtk_t7xx(+) qcserial pppoe ppp_async option nft_fib_inet nf_flow_table_inet mt7921u(O) mt7921s(O) mt7921e(O) mt7921_common(O) iwlmvm(O) iwldvm(O) usb_wwan rndis_host qmi_wwan pppox ppp_generic nft_reject_ipv6 nft_reject_ipv4 nft_reject_inet nft_reject nft_redir nft_quota nft_numgen nft_nat nft_masq nft_log nft_limit nft_hash nft_flow_offload nft_fib_ipv6 nft_fib_ipv4 nft_fib nft_ct nft_chain_nat nf_tables nf_nat nf_flow_table nf_conntrack mt7996e(O) mt792x_usb(O) mt792x_lib(O) mt7915e(O) mt76_usb(O) mt76_sdio(O) mt76_connac_lib(O) mt76(O) mac80211(O) iwlwifi(O) huawei_cdc_ncm cfg80211(O) cdc_ncm cdc_ether wwan usbserial usbnet slhc sfp rtc_pcf8563 nfnetlink nf_reject_ipv6 nf_reject_ipv4 nf_log_syslog nf_defrag_ipv6 nf_defrag_ipv4 mt6577_auxadc mdio_i2c libcrc32c compat(O) cdc_wdm cdc_acm at24 crypto_safexcel pwm_fan i2c_gpio i2c_smbus industrialio i2c_algo_bit i2c_mux_reg i2c_mux_pca954x i2c_mux_pca9541 i2c_mux_gpio i2c_mux dummy oid_registry tun sha512_arm64 sha1_ce sha1_generic seqiv
md5 geniv des_generic libdes cbc authencesn authenc leds_gpio xhci_plat_hcd xhci_pci xhci_mtk_hcd xhci_hcd nvme nvme_core gpio_button_hotplug(O) dm_mirror dm_region_hash dm_log dm_crypt dm_mod dax usbcore usb_common ptp aquantia pps_core mii tpm encrypted_keys trusted
CPU: 3 PID: 5266 Comm: kworker/u9:1 Tainted: G O 6.6.22 #0
Hardware name: Bananapi BPI-R4 (DT)
Workqueue: md_hk_wq t7xx_fsm_uninit [mtk_t7xx]
pstate: 804000c5 (Nzcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : t7xx_cldma_hw_set_start_addr+0x1c/0x3c [mtk_t7xx]
lr : t7xx_cldma_start+0xac/0x13c [mtk_t7xx]
sp : ffffffc085d63d30
x29: ffffffc085d63d30 x28: 0000000000000000 x27: 0000000000000000
x26: 0000000000000000 x25: ffffff80c804f2c0 x24: ffffff80ca196c05
x23: 0000000000000000 x22: ffffff80c814b9b8 x21: ffffff80c814b128
x20: 0000000000000001 x19: ffffff80c814b080 x18: 0000000000000014
x17: 0000000055c9806b x16: 000000007c5296d0 x15: 000000000f6bca68
x14: 00000000dbdbdce4 x13: 000000001aeaf72a x12: 0000000000000001
x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000
x8 : ffffff80ca1ef6b4 x7 : ffffff80c814b818 x6 : 0000000000000018
x5 : 0000000000000870 x4 : 0000000000000000 x3 : 0000000000000000
x2 : 000000010a947000 x1 : ffffffc084a1d004 x0 : ffffffc084a1d004
Call trace:
t7xx_cldma_hw_set_start_addr+0x1c/0x3c [mtk_t7xx]
t7xx_fsm_uninit+0x578/0x5ec [mtk_t7xx]
process_one_work+0x154/0x2a0
worker_thread+0x2ac/0x488
kthread+0xe0/0xec
ret_from_fork+0x10/0x20
Code: f9400800 91001000 8b214001 d50332bf (f9000022)
---[ end trace 0000000000000000 ]---
The inclusion of io-64-nonatomic-lo-hi.h indicates that all 64bit
accesses can be replaced by pairs of nonatomic 32bit access. Fix
alignment by forcing all accesses to be 32bit on 64bit platforms.
Link: https://forum.openwrt.org/t/fibocom-fm350-gl-support/142682/72
Fixes: 39d439047f ("net: wwan: t7xx: Add control DMA interface")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Tested-by: Liviu Dudau <liviu@dudau.co.uk>
Link: https://lore.kernel.org/r/20240322144000.1683822-1-bjorn@mork.no
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
282 lines
8.3 KiB
C
282 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Eliot Lee <eliot.lee@intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*/
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/types.h>
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#include "t7xx_cldma.h"
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#define ADDR_SIZE 8
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void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info)
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{
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u32 val;
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val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
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val |= IP_BUSY_WAKEUP;
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iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
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}
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/**
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* t7xx_cldma_hw_restore() - Restore CLDMA HW registers.
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* @hw_info: Pointer to struct t7xx_cldma_hw.
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*
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* Restore HW after resume. Writes uplink configuration for CLDMA HW.
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*/
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void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info)
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{
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u32 ul_cfg;
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ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
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if (hw_info->hw_mode == MODE_BIT_64)
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ul_cfg |= UL_CFG_BIT_MODE_64;
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else if (hw_info->hw_mode == MODE_BIT_40)
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ul_cfg |= UL_CFG_BIT_MODE_40;
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else if (hw_info->hw_mode == MODE_BIT_36)
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ul_cfg |= UL_CFG_BIT_MODE_36;
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iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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/* Disable TX and RX invalid address check */
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iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
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iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
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}
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void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :
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hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val, reg);
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}
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void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info)
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{
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/* Enable the TX & RX interrupts */
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iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
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iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
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/* Enable the empty queue interrupt */
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iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
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iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
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}
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void t7xx_cldma_hw_reset(void __iomem *ao_base)
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{
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u32 val;
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val = ioread32(ao_base + REG_INFRA_RST2_SET);
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val |= RST2_PMIC_SW_RST_SET;
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iowrite32(val, ao_base + REG_INFRA_RST2_SET);
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val = ioread32(ao_base + REG_INFRA_RST4_SET);
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val |= RST4_CLDMA1_SW_RST_SET;
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iowrite32(val, ao_base + REG_INFRA_RST4_SET);
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udelay(1);
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val = ioread32(ao_base + REG_INFRA_RST4_CLR);
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val |= RST4_CLDMA1_SW_RST_CLR;
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iowrite32(val, ao_base + REG_INFRA_RST4_CLR);
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val = ioread32(ao_base + REG_INFRA_RST2_CLR);
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val |= RST2_PMIC_SW_RST_CLR;
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iowrite32(val, ao_base + REG_INFRA_RST2_CLR);
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}
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bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno)
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{
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u32 offset = REG_CLDMA_UL_START_ADDRL_0 + qno * ADDR_SIZE;
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return ioread64_lo_hi(hw_info->ap_pdn_base + offset);
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}
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void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address,
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enum mtk_txrx tx_rx)
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{
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u32 offset = qno * ADDR_SIZE;
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void __iomem *reg;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_START_ADDRL_0 :
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hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0;
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iowrite64_lo_hi(address, reg + offset);
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}
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void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *base = hw_info->ap_pdn_base;
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if (tx_rx == MTK_RX)
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iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD);
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else
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iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD);
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}
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unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 mask, val;
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mask = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_STATUS :
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hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS;
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val = ioread32(reg);
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return val & mask;
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}
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void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
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{
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unsigned int ch_id;
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ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
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ch_id &= bitmask;
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/* Clear the ch IDs in the TX interrupt status register */
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iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
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ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
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}
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void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
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{
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unsigned int ch_id;
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ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
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ch_id &= bitmask;
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/* Clear the ch IDs in the RX interrupt status register */
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iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
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ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
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}
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unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0;
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val = ioread32(reg);
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return val & bitmask;
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}
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void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val, reg);
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}
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void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val << EQ_STA_BIT_OFFSET, reg);
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}
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void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val, reg);
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}
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void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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u32 val;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
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val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
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iowrite32(val << EQ_STA_BIT_OFFSET, reg);
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}
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/**
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* t7xx_cldma_hw_init() - Initialize CLDMA HW.
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* @hw_info: Pointer to struct t7xx_cldma_hw.
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*
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* Write uplink and downlink configuration to CLDMA HW.
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*/
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void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info)
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{
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u32 ul_cfg, dl_cfg;
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ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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dl_cfg = ioread32(hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
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/* Configure the DRAM address mode */
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ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
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dl_cfg &= ~DL_CFG_BIT_MODE_MASK;
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if (hw_info->hw_mode == MODE_BIT_64) {
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ul_cfg |= UL_CFG_BIT_MODE_64;
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dl_cfg |= DL_CFG_BIT_MODE_64;
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} else if (hw_info->hw_mode == MODE_BIT_40) {
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ul_cfg |= UL_CFG_BIT_MODE_40;
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dl_cfg |= DL_CFG_BIT_MODE_40;
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} else if (hw_info->hw_mode == MODE_BIT_36) {
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ul_cfg |= UL_CFG_BIT_MODE_36;
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dl_cfg |= DL_CFG_BIT_MODE_36;
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}
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iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
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dl_cfg |= DL_CFG_UP_HW_LAST;
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iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
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iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK);
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iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK);
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iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
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iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
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}
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void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD :
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hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD;
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iowrite32(CLDMA_ALL_Q, reg);
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}
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void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
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{
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void __iomem *reg;
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reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
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hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
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iowrite32(TXRX_STATUS_BITMASK, reg);
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iowrite32(EMPTY_STATUS_BITMASK, reg);
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}
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