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1d2709d6d3
As a general policy, we refer our generic register definitions over vendor specific definitions. In XPCS, it appears that the register layout follows a BMCR, BMSR and ADVERTISE register definition. We already refer to this BMCR register using several different macros which is confusing. Convert the following register definitions to generic versions: DW_VR_MII_MMD_CTRL => MII_BMCR MDIO_CTRL1 => MII_BMCR AN_CL37_EN => BMCR_ANENABLE SGMII_SPEED_SS6 => BMCR_SPEED1000 SGMII_SPEED_SS13 => BMCR_SPEED100 MDIO_CTRL1_RESET => BMCR_RESET DW_VR_MII_MMD_STS => MII_BMSR DW_VR_MII_MMD_STS_LINK_STS => BMSR_LSTATUS DW_FULL_DUPLEX => ADVERTISE_1000XFULL iDW_HALF_DUPLEX => ADVERTISE_1000XHALF Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Tested-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare XPCS helpers
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*
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* Author: Jose Abreu <Jose.Abreu@synopsys.com>
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*/
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#include <linux/bits.h>
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#include <linux/pcs/pcs-xpcs.h>
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/* Vendor regs access */
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#define DW_VENDOR BIT(15)
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/* VR_XS_PCS */
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#define DW_USXGMII_RST BIT(10)
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#define DW_USXGMII_EN BIT(9)
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#define DW_VR_XS_PCS_DIG_CTRL1 0x0000
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#define DW_VR_RST BIT(15)
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#define DW_EN_VSMMD1 BIT(13)
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#define DW_CL37_BP BIT(12)
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#define DW_VR_XS_PCS_DIG_STS 0x0010
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#define DW_RXFIFO_ERR GENMASK(6, 5)
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#define DW_PSEQ_ST GENMASK(4, 2)
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#define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4)
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/* SR_MII */
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#define DW_USXGMII_FULL BIT(8)
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#define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5))
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#define DW_USXGMII_10000 (BIT(13) | BIT(6))
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#define DW_USXGMII_5000 (BIT(13) | BIT(5))
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#define DW_USXGMII_2500 (BIT(5))
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#define DW_USXGMII_1000 (BIT(6))
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#define DW_USXGMII_100 (BIT(13))
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#define DW_USXGMII_10 (0)
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/* SR_AN */
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#define DW_SR_AN_ADV1 0x10
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#define DW_SR_AN_ADV2 0x11
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#define DW_SR_AN_ADV3 0x12
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/* Clause 73 Defines */
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/* AN_LP_ABL1 */
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#define DW_C73_PAUSE BIT(10)
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#define DW_C73_ASYM_PAUSE BIT(11)
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#define DW_C73_AN_ADV_SF 0x1
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/* AN_LP_ABL2 */
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#define DW_C73_1000KX BIT(5)
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#define DW_C73_10000KX4 BIT(6)
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#define DW_C73_10000KR BIT(7)
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/* AN_LP_ABL3 */
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#define DW_C73_2500KX BIT(0)
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#define DW_C73_5000KR BIT(1)
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/* Clause 37 Defines */
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/* VR MII MMD registers offsets */
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#define DW_VR_MII_DIG_CTRL1 0x8000
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#define DW_VR_MII_AN_CTRL 0x8001
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#define DW_VR_MII_AN_INTR_STS 0x8002
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/* EEE Mode Control Register */
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#define DW_VR_MII_EEE_MCTRL0 0x8006
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#define DW_VR_MII_EEE_MCTRL1 0x800b
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#define DW_VR_MII_DIG_CTRL2 0x80e1
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/* VR_MII_DIG_CTRL1 */
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#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
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#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
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#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0)
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/* VR_MII_DIG_CTRL2 */
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#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
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#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0)
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/* VR_MII_AN_CTRL */
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#define DW_VR_MII_AN_CTRL_8BIT BIT(8)
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#define DW_VR_MII_TX_CONFIG_MASK BIT(3)
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#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1
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#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0
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#define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1)
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#define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0
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#define DW_VR_MII_PCS_MODE_C37_SGMII 0x2
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#define DW_VR_MII_AN_INTR_EN BIT(0)
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/* VR_MII_AN_INTR_STS */
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#define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0)
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#define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1)
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#define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2)
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#define DW_VR_MII_C37_ANSGM_SP_10 0x0
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#define DW_VR_MII_C37_ANSGM_SP_100 0x1
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#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
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#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
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/* VR MII EEE Control 0 defines */
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#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
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#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
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#define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */
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#define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */
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#define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */
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#define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */
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#define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8)
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/* VR MII EEE Control 1 defines */
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#define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */
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#define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \
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static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }
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struct dw_xpcs_desc;
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enum dw_xpcs_clock {
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DW_XPCS_CORE_CLK,
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DW_XPCS_PAD_CLK,
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DW_XPCS_NUM_CLKS,
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};
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struct dw_xpcs {
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struct dw_xpcs_info info;
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const struct dw_xpcs_desc *desc;
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struct mdio_device *mdiodev;
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struct clk_bulk_data clks[DW_XPCS_NUM_CLKS];
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struct phylink_pcs pcs;
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phy_interface_t interface;
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bool need_reset;
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};
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int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
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int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
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int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set);
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int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg);
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int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val);
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int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
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int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
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int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);
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int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface);
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