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This patch adds supports for multiple PHY hardware with phylink. The adapters with TN40xx chips use multiple PHY hardware; AMCC QT2025, TI TLK10232, Aqrate AQR105, and Marvell 88X3120, 88X3310, and MV88E2010. For now, the PCI ID table of this driver enables adapters using only QT2025 PHY. I've tested this driver and the QT2025 PHY driver (SFP+ 10G SR) with Edimax EN-9320 10G adapter. Signed-off-by: FUJITA Tomonori <fujita.tomonori@gmail.com> Reviewed-by: Hans-Frieder Vogt <hfdevel@gmx.net> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/20240623235507.108147-8-fujita.tomonori@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (c) Tehuti Networks Ltd. */
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/phylink.h>
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#include "tn40.h"
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static struct tn40_priv *tn40_config_to_priv(struct phylink_config *config)
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{
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return container_of(config, struct tn40_priv, phylink_config);
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}
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static void tn40_link_up(struct phylink_config *config, struct phy_device *phy,
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unsigned int mode, phy_interface_t interface,
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int speed, int duplex, bool tx_pause, bool rx_pause)
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{
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struct tn40_priv *priv = tn40_config_to_priv(config);
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tn40_set_link_speed(priv, speed);
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netif_wake_queue(priv->ndev);
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}
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static void tn40_link_down(struct phylink_config *config, unsigned int mode,
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phy_interface_t interface)
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{
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struct tn40_priv *priv = tn40_config_to_priv(config);
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netif_stop_queue(priv->ndev);
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tn40_set_link_speed(priv, 0);
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}
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static void tn40_mac_config(struct phylink_config *config, unsigned int mode,
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const struct phylink_link_state *state)
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{
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}
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static const struct phylink_mac_ops tn40_mac_ops = {
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.mac_config = tn40_mac_config,
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.mac_link_up = tn40_link_up,
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.mac_link_down = tn40_link_down,
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};
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int tn40_phy_register(struct tn40_priv *priv)
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{
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struct phylink_config *config;
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struct phy_device *phydev;
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struct phylink *phylink;
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phydev = phy_find_first(priv->mdio);
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if (!phydev) {
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dev_err(&priv->pdev->dev, "PHY isn't found\n");
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return -ENODEV;
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}
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config = &priv->phylink_config;
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config->dev = &priv->ndev->dev;
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config->type = PHYLINK_NETDEV;
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config->mac_capabilities = MAC_10000FD;
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__set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);
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phylink = phylink_create(config, NULL, PHY_INTERFACE_MODE_XAUI,
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&tn40_mac_ops);
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if (IS_ERR(phylink))
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return PTR_ERR(phylink);
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priv->phydev = phydev;
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priv->phylink = phylink;
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return 0;
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}
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void tn40_phy_unregister(struct tn40_priv *priv)
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{
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phylink_destroy(priv->phylink);
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}
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