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Add driver for the Qualcomm interconnect buses found in X1E80100 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231123135028.29433-3-quic_sibis@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
193 lines
7.2 KiB
C
193 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* X1E80100 interconnect IDs
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*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
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#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
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#define X1E80100_MASTER_A1NOC_SNOC 0
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#define X1E80100_MASTER_A2NOC_SNOC 1
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#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2
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#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3
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#define X1E80100_MASTER_APPSS_PROC 4
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#define X1E80100_MASTER_CAMNOC_HF 5
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#define X1E80100_MASTER_CAMNOC_ICP 6
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#define X1E80100_MASTER_CAMNOC_SF 7
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#define X1E80100_MASTER_CDSP_PROC 8
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#define X1E80100_MASTER_CNOC_CFG 9
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#define X1E80100_MASTER_CNOC_MNOC_CFG 10
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#define X1E80100_MASTER_COMPUTE_NOC 11
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#define X1E80100_MASTER_CRYPTO 12
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#define X1E80100_MASTER_GEM_NOC_CNOC 13
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#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14
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#define X1E80100_MASTER_GFX3D 15
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#define X1E80100_MASTER_GPU_TCU 16
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#define X1E80100_MASTER_IPA 17
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#define X1E80100_MASTER_LLCC 18
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#define X1E80100_MASTER_LLCC_DISP 19
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#define X1E80100_MASTER_LPASS_GEM_NOC 20
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#define X1E80100_MASTER_LPASS_LPINOC 21
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#define X1E80100_MASTER_LPASS_PROC 22
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#define X1E80100_MASTER_LPIAON_NOC 23
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#define X1E80100_MASTER_MDP 24
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#define X1E80100_MASTER_MDP_DISP 25
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#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26
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#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27
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#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28
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#define X1E80100_MASTER_PCIE_0 29
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#define X1E80100_MASTER_PCIE_1 30
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#define X1E80100_MASTER_QDSS_ETR 31
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#define X1E80100_MASTER_QDSS_ETR_1 32
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#define X1E80100_MASTER_QSPI_0 33
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#define X1E80100_MASTER_QUP_0 34
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#define X1E80100_MASTER_QUP_1 35
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#define X1E80100_MASTER_QUP_2 36
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#define X1E80100_MASTER_QUP_CORE_0 37
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#define X1E80100_MASTER_QUP_CORE_1 38
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#define X1E80100_MASTER_SDCC_2 39
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#define X1E80100_MASTER_SDCC_4 40
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#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41
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#define X1E80100_MASTER_SP 42
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#define X1E80100_MASTER_SYS_TCU 43
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#define X1E80100_MASTER_UFS_MEM 44
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#define X1E80100_MASTER_USB3_0 45
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#define X1E80100_MASTER_VIDEO 46
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#define X1E80100_MASTER_VIDEO_CV_PROC 47
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#define X1E80100_MASTER_VIDEO_V_PROC 48
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#define X1E80100_SLAVE_A1NOC_SNOC 49
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#define X1E80100_SLAVE_A2NOC_SNOC 50
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#define X1E80100_SLAVE_AHB2PHY_NORTH 51
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#define X1E80100_SLAVE_AHB2PHY_SOUTH 52
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#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53
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#define X1E80100_SLAVE_AOSS 54
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#define X1E80100_SLAVE_APPSS 55
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#define X1E80100_SLAVE_BOOT_IMEM 56
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#define X1E80100_SLAVE_CAMERA_CFG 57
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#define X1E80100_SLAVE_CDSP_MEM_NOC 58
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#define X1E80100_SLAVE_CLK_CTL 59
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#define X1E80100_SLAVE_CNOC_CFG 60
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#define X1E80100_SLAVE_CNOC_MNOC_CFG 61
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#define X1E80100_SLAVE_CRYPTO_0_CFG 62
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#define X1E80100_SLAVE_DISPLAY_CFG 63
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#define X1E80100_SLAVE_EBI1 64
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#define X1E80100_SLAVE_EBI1_DISP 65
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#define X1E80100_SLAVE_GEM_NOC_CNOC 66
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#define X1E80100_SLAVE_GFX3D_CFG 67
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#define X1E80100_SLAVE_IMEM 68
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#define X1E80100_SLAVE_IMEM_CFG 69
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#define X1E80100_SLAVE_IPC_ROUTER_CFG 70
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#define X1E80100_SLAVE_LLCC 71
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#define X1E80100_SLAVE_LLCC_DISP 72
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#define X1E80100_SLAVE_LPASS_GEM_NOC 73
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#define X1E80100_SLAVE_LPASS_QTB_CFG 74
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#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75
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#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76
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#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77
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#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78
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#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79
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#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80
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#define X1E80100_SLAVE_NSP_QTB_CFG 81
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#define X1E80100_SLAVE_PCIE_0 82
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#define X1E80100_SLAVE_PCIE_0_CFG 83
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#define X1E80100_SLAVE_PCIE_1 84
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#define X1E80100_SLAVE_PCIE_1_CFG 85
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#define X1E80100_SLAVE_PDM 86
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#define X1E80100_SLAVE_PRNG 87
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#define X1E80100_SLAVE_QDSS_CFG 88
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#define X1E80100_SLAVE_QDSS_STM 89
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#define X1E80100_SLAVE_QSPI_0 90
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#define X1E80100_SLAVE_QUP_1 91
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#define X1E80100_SLAVE_QUP_2 92
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#define X1E80100_SLAVE_QUP_CORE_0 93
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#define X1E80100_SLAVE_QUP_CORE_1 94
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#define X1E80100_SLAVE_QUP_CORE_2 95
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#define X1E80100_SLAVE_SDCC_2 96
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#define X1E80100_SLAVE_SDCC_4 97
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#define X1E80100_SLAVE_SERVICE_MNOC 98
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#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99
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#define X1E80100_SLAVE_TCSR 100
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#define X1E80100_SLAVE_TCU 101
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#define X1E80100_SLAVE_TLMM 102
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#define X1E80100_SLAVE_TME_CFG 103
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#define X1E80100_SLAVE_UFS_MEM_CFG 104
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#define X1E80100_SLAVE_USB3_0 105
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#define X1E80100_SLAVE_VENUS_CFG 106
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#define X1E80100_MASTER_DDR_PERF_MODE 107
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#define X1E80100_MASTER_QUP_CORE_2 108
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#define X1E80100_MASTER_PCIE_TCU 109
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#define X1E80100_MASTER_GIC2 110
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#define X1E80100_MASTER_AV1_ENC 111
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#define X1E80100_MASTER_EVA 112
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#define X1E80100_MASTER_PCIE_NORTH 113
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#define X1E80100_MASTER_PCIE_SOUTH 114
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#define X1E80100_MASTER_PCIE_3 115
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#define X1E80100_MASTER_PCIE_4 116
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#define X1E80100_MASTER_PCIE_5 117
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#define X1E80100_MASTER_PCIE_2 118
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#define X1E80100_MASTER_PCIE_6A 119
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#define X1E80100_MASTER_PCIE_6B 120
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#define X1E80100_MASTER_GIC1 121
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#define X1E80100_MASTER_USB_NOC_SNOC 122
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#define X1E80100_MASTER_AGGRE_USB_NORTH 123
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#define X1E80100_MASTER_AGGRE_USB_SOUTH 124
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#define X1E80100_MASTER_USB2 125
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#define X1E80100_MASTER_USB3_MP 126
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#define X1E80100_MASTER_USB3_1 127
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#define X1E80100_MASTER_USB3_2 128
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#define X1E80100_MASTER_USB4_0 129
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#define X1E80100_MASTER_USB4_1 130
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#define X1E80100_MASTER_USB4_2 131
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#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132
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#define X1E80100_MASTER_LLCC_PCIE 133
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#define X1E80100_MASTER_PCIE_NORTH_PCIE 134
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#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135
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#define X1E80100_MASTER_PCIE_3_PCIE 136
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#define X1E80100_MASTER_PCIE_4_PCIE 137
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#define X1E80100_MASTER_PCIE_5_PCIE 138
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#define X1E80100_MASTER_PCIE_0_PCIE 139
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#define X1E80100_MASTER_PCIE_1_PCIE 140
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#define X1E80100_MASTER_PCIE_2_PCIE 141
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#define X1E80100_MASTER_PCIE_6A_PCIE 142
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#define X1E80100_MASTER_PCIE_6B_PCIE 143
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#define X1E80100_SLAVE_AHB2PHY_2 144
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#define X1E80100_SLAVE_AV1_ENC_CFG 145
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#define X1E80100_SLAVE_PCIE_2_CFG 146
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#define X1E80100_SLAVE_PCIE_3_CFG 147
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#define X1E80100_SLAVE_PCIE_4_CFG 148
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#define X1E80100_SLAVE_PCIE_5_CFG 149
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#define X1E80100_SLAVE_PCIE_6A_CFG 150
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#define X1E80100_SLAVE_PCIE_6B_CFG 151
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#define X1E80100_SLAVE_PCIE_RSC_CFG 152
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#define X1E80100_SLAVE_QUP_0 153
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#define X1E80100_SLAVE_SMMUV3_CFG 154
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#define X1E80100_SLAVE_USB2 155
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#define X1E80100_SLAVE_USB3_1 156
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#define X1E80100_SLAVE_USB3_2 157
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#define X1E80100_SLAVE_USB3_MP 158
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#define X1E80100_SLAVE_USB4_0 159
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#define X1E80100_SLAVE_USB4_1 160
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#define X1E80100_SLAVE_USB4_2 161
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#define X1E80100_SLAVE_PCIE_2 162
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#define X1E80100_SLAVE_PCIE_3 163
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#define X1E80100_SLAVE_PCIE_4 164
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#define X1E80100_SLAVE_PCIE_5 165
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#define X1E80100_SLAVE_PCIE_6A 166
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#define X1E80100_SLAVE_PCIE_6B 167
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#define X1E80100_SLAVE_DDR_PERF_MODE 168
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#define X1E80100_SLAVE_PCIE_NORTH 169
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#define X1E80100_SLAVE_PCIE_SOUTH 170
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#define X1E80100_SLAVE_USB_NOC_SNOC 171
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#define X1E80100_SLAVE_AGGRE_USB_NORTH 172
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#define X1E80100_SLAVE_AGGRE_USB_SOUTH 173
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#define X1E80100_SLAVE_LLCC_PCIE 174
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#define X1E80100_SLAVE_EBI1_PCIE 175
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#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE 176
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#define X1E80100_SLAVE_PCIE_NORTH_PCIE 177
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#define X1E80100_SLAVE_PCIE_SOUTH_PCIE 178
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#endif
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