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cde2f928ae
The QUP0 BCM relates to some internal property of the QUPs, and should
be configured independently of the path to the QUP. In line with other
platforms expose QUP_CORE endpoints in order allow this configuration.
Fixes: 6df5b34949 ("interconnect: qcom: Add SM8250 interconnect provider driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230703-topic-8250_qup_icc-v2-3-9ba0a9460be2@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
169 lines
5.9 KiB
C
169 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Qualcomm #define SM8250 interconnect IDs
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*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
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#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
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#define SM8250_A1NOC_SNOC_MAS 0
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#define SM8250_A1NOC_SNOC_SLV 1
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#define SM8250_A2NOC_SNOC_MAS 2
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#define SM8250_A2NOC_SNOC_SLV 3
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#define SM8250_MASTER_A1NOC_CFG 4
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#define SM8250_MASTER_A2NOC_CFG 5
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#define SM8250_MASTER_AMPSS_M0 6
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#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7
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#define SM8250_MASTER_CAMNOC_HF 8
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#define SM8250_MASTER_CAMNOC_ICP 9
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#define SM8250_MASTER_CAMNOC_SF 10
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#define SM8250_MASTER_CNOC_A2NOC 11
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#define SM8250_MASTER_CNOC_DC_NOC 12
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#define SM8250_MASTER_CNOC_MNOC_CFG 13
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#define SM8250_MASTER_COMPUTE_NOC 14
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#define SM8250_MASTER_CRYPTO_CORE_0 15
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#define SM8250_MASTER_GEM_NOC_CFG 16
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#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17
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#define SM8250_MASTER_GEM_NOC_SNOC 18
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#define SM8250_MASTER_GIC 19
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#define SM8250_MASTER_GPU_TCU 20
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#define SM8250_MASTER_GRAPHICS_3D 21
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#define SM8250_MASTER_IPA 22
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/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
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#define SM8250_MASTER_LLCC 24
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#define SM8250_MASTER_MDP_PORT0 25
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#define SM8250_MASTER_MDP_PORT1 26
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#define SM8250_MASTER_MNOC_HF_MEM_NOC 27
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#define SM8250_MASTER_MNOC_SF_MEM_NOC 28
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#define SM8250_MASTER_NPU 29
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#define SM8250_MASTER_NPU_CDP 30
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#define SM8250_MASTER_NPU_NOC_CFG 31
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#define SM8250_MASTER_NPU_SYS 32
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#define SM8250_MASTER_PCIE 33
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#define SM8250_MASTER_PCIE_1 34
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#define SM8250_MASTER_PCIE_2 35
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#define SM8250_MASTER_PIMEM 36
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#define SM8250_MASTER_QDSS_BAM 37
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#define SM8250_MASTER_QDSS_DAP 38
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#define SM8250_MASTER_QDSS_ETR 39
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#define SM8250_MASTER_QSPI_0 40
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#define SM8250_MASTER_QUP_0 41
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#define SM8250_MASTER_QUP_1 42
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#define SM8250_MASTER_QUP_2 43
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#define SM8250_MASTER_ROTATOR 44
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#define SM8250_MASTER_SDCC_2 45
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#define SM8250_MASTER_SDCC_4 46
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#define SM8250_MASTER_SNOC_CFG 47
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#define SM8250_MASTER_SNOC_GC_MEM_NOC 48
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#define SM8250_MASTER_SNOC_SF_MEM_NOC 49
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#define SM8250_MASTER_SYS_TCU 50
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#define SM8250_MASTER_TSIF 51
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#define SM8250_MASTER_UFS_CARD 52
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#define SM8250_MASTER_UFS_MEM 53
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#define SM8250_MASTER_USB3 54
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#define SM8250_MASTER_USB3_1 55
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#define SM8250_MASTER_VIDEO_P0 56
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#define SM8250_MASTER_VIDEO_P1 57
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#define SM8250_MASTER_VIDEO_PROC 58
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#define SM8250_SLAVE_A1NOC_CFG 59
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#define SM8250_SLAVE_A2NOC_CFG 60
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#define SM8250_SLAVE_AHB2PHY_NORTH 61
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#define SM8250_SLAVE_AHB2PHY_SOUTH 62
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#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63
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#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64
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#define SM8250_SLAVE_AOSS 65
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#define SM8250_SLAVE_APPSS 66
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#define SM8250_SLAVE_CAMERA_CFG 67
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#define SM8250_SLAVE_CDSP_CFG 68
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#define SM8250_SLAVE_CDSP_MEM_NOC 69
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#define SM8250_SLAVE_CLK_CTL 70
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#define SM8250_SLAVE_CNOC_A2NOC 71
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#define SM8250_SLAVE_CNOC_DDRSS 72
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#define SM8250_SLAVE_CNOC_MNOC_CFG 73
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#define SM8250_SLAVE_CRYPTO_0_CFG 74
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#define SM8250_SLAVE_CX_RDPM 75
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#define SM8250_SLAVE_DCC_CFG 76
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#define SM8250_SLAVE_DISPLAY_CFG 77
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#define SM8250_SLAVE_EBI_CH0 78
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#define SM8250_SLAVE_GEM_NOC_CFG 79
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#define SM8250_SLAVE_GEM_NOC_SNOC 80
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#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
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#define SM8250_SLAVE_IMEM_CFG 82
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#define SM8250_SLAVE_IPA_CFG 83
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/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SM8250_SLAVE_IPC_ROUTER_CFG 85
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#define SM8250_SLAVE_ISENSE_CFG 86
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#define SM8250_SLAVE_LLCC 87
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#define SM8250_SLAVE_LLCC_CFG 88
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#define SM8250_SLAVE_LPASS 89
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#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90
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#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91
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#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92
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#define SM8250_SLAVE_NPU_CAL_DP0 93
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#define SM8250_SLAVE_NPU_CAL_DP1 94
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#define SM8250_SLAVE_NPU_CFG 95
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#define SM8250_SLAVE_NPU_COMPUTE_NOC 96
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#define SM8250_SLAVE_NPU_CP 97
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#define SM8250_SLAVE_NPU_DPM 98
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#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99
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#define SM8250_SLAVE_NPU_LLM_CFG 100
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#define SM8250_SLAVE_NPU_TCM 101
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#define SM8250_SLAVE_OCIMEM 102
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#define SM8250_SLAVE_PCIE_0 103
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#define SM8250_SLAVE_PCIE_0_CFG 104
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#define SM8250_SLAVE_PCIE_1 105
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#define SM8250_SLAVE_PCIE_1_CFG 106
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#define SM8250_SLAVE_PCIE_2 107
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#define SM8250_SLAVE_PCIE_2_CFG 108
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#define SM8250_SLAVE_PDM 109
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#define SM8250_SLAVE_PIMEM 110
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#define SM8250_SLAVE_PIMEM_CFG 111
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#define SM8250_SLAVE_PRNG 112
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#define SM8250_SLAVE_QDSS_CFG 113
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#define SM8250_SLAVE_QDSS_STM 114
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#define SM8250_SLAVE_QSPI_0 115
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#define SM8250_SLAVE_QUP_0 116
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#define SM8250_SLAVE_QUP_1 117
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#define SM8250_SLAVE_QUP_2 118
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#define SM8250_SLAVE_RBCPR_CX_CFG 119
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#define SM8250_SLAVE_RBCPR_MMCX_CFG 120
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#define SM8250_SLAVE_RBCPR_MX_CFG 121
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#define SM8250_SLAVE_SDCC_2 122
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#define SM8250_SLAVE_SDCC_4 123
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#define SM8250_SLAVE_SERVICE_A1NOC 124
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#define SM8250_SLAVE_SERVICE_A2NOC 125
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#define SM8250_SLAVE_SERVICE_CNOC 126
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#define SM8250_SLAVE_SERVICE_GEM_NOC 127
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#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128
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#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129
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#define SM8250_SLAVE_SERVICE_MNOC 130
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#define SM8250_SLAVE_SERVICE_NPU_NOC 131
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#define SM8250_SLAVE_SERVICE_SNOC 132
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#define SM8250_SLAVE_SNOC_CFG 133
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#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134
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#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135
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#define SM8250_SLAVE_TCSR 136
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#define SM8250_SLAVE_TCU 137
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#define SM8250_SLAVE_TLMM_NORTH 138
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#define SM8250_SLAVE_TLMM_SOUTH 139
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#define SM8250_SLAVE_TLMM_WEST 140
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#define SM8250_SLAVE_TSIF 141
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#define SM8250_SLAVE_UFS_CARD_CFG 142
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#define SM8250_SLAVE_UFS_MEM_CFG 143
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#define SM8250_SLAVE_USB3 144
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#define SM8250_SLAVE_USB3_1 145
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#define SM8250_SLAVE_VENUS_CFG 146
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#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
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#define SM8250_SNOC_CNOC_MAS 148
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#define SM8250_SNOC_CNOC_SLV 149
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#define SM8250_MASTER_QUP_CORE_0 150
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#define SM8250_MASTER_QUP_CORE_1 151
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#define SM8250_MASTER_QUP_CORE_2 152
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#define SM8250_SLAVE_QUP_CORE_0 153
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#define SM8250_SLAVE_QUP_CORE_1 154
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#define SM8250_SLAVE_QUP_CORE_2 155
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#endif
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