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6ffa9bd6eb
This reverts commit 767bfb9ef27ebf760290d9f8bc303828b018c312. It appears that the call of ohci_flush_iso_completions() in the work item scheduled by hardIRQ of 1394 OHCI for any isochronous context changes the timing to queue events in the view of user space application. Link: https://lore.kernel.org/r/20240912133038.238786-3-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
293 lines
7.9 KiB
C
293 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _FIREWIRE_CORE_H
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#define _FIREWIRE_CORE_H
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#include <linux/compiler.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/fs.h>
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#include <linux/list.h>
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#include <linux/xarray.h>
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#include <linux/mm_types.h>
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#include <linux/rwsem.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/refcount.h>
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struct device;
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struct fw_card;
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struct fw_device;
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struct fw_iso_buffer;
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struct fw_iso_context;
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struct fw_iso_packet;
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struct fw_node;
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struct fw_packet;
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/* -card */
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extern __printf(2, 3)
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void fw_err(const struct fw_card *card, const char *fmt, ...);
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extern __printf(2, 3)
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void fw_notice(const struct fw_card *card, const char *fmt, ...);
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/* bitfields within the PHY registers */
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#define PHY_LINK_ACTIVE 0x80
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#define PHY_CONTENDER 0x40
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#define PHY_BUS_RESET 0x40
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#define PHY_EXTENDED_REGISTERS 0xe0
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#define PHY_BUS_SHORT_RESET 0x40
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#define PHY_INT_STATUS_BITS 0x3c
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#define PHY_ENABLE_ACCEL 0x02
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#define PHY_ENABLE_MULTI 0x01
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#define PHY_PAGE_SELECT 0xe0
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#define BANDWIDTH_AVAILABLE_INITIAL 4915
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#define BROADCAST_CHANNEL_INITIAL (1 << 31 | 31)
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#define BROADCAST_CHANNEL_VALID (1 << 30)
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#define CSR_STATE_BIT_CMSTR (1 << 8)
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#define CSR_STATE_BIT_ABDICATE (1 << 10)
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struct fw_card_driver {
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/*
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* Enable the given card with the given initial config rom.
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* This function is expected to activate the card, and either
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* enable the PHY or set the link_on bit and initiate a bus
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* reset.
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*/
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int (*enable)(struct fw_card *card,
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const __be32 *config_rom, size_t length);
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int (*read_phy_reg)(struct fw_card *card, int address);
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int (*update_phy_reg)(struct fw_card *card, int address,
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int clear_bits, int set_bits);
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/*
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* Update the config rom for an enabled card. This function
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* should change the config rom that is presented on the bus
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* and initiate a bus reset.
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*/
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int (*set_config_rom)(struct fw_card *card,
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const __be32 *config_rom, size_t length);
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void (*send_request)(struct fw_card *card, struct fw_packet *packet);
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void (*send_response)(struct fw_card *card, struct fw_packet *packet);
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/* Calling cancel is valid once a packet has been submitted. */
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int (*cancel_packet)(struct fw_card *card, struct fw_packet *packet);
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/*
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* Allow the specified node ID to do direct DMA out and in of
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* host memory. The card will disable this for all node when
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* a bus reset happens, so driver need to reenable this after
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* bus reset. Returns 0 on success, -ENODEV if the card
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* doesn't support this, -ESTALE if the generation doesn't
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* match.
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*/
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int (*enable_phys_dma)(struct fw_card *card,
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int node_id, int generation);
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u32 (*read_csr)(struct fw_card *card, int csr_offset);
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void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
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struct fw_iso_context *
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(*allocate_iso_context)(struct fw_card *card,
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int type, int channel, size_t header_size);
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void (*free_iso_context)(struct fw_iso_context *ctx);
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int (*start_iso)(struct fw_iso_context *ctx,
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s32 cycle, u32 sync, u32 tags);
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int (*set_iso_channels)(struct fw_iso_context *ctx, u64 *channels);
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int (*queue_iso)(struct fw_iso_context *ctx,
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struct fw_iso_packet *packet,
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struct fw_iso_buffer *buffer,
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unsigned long payload);
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void (*flush_queue_iso)(struct fw_iso_context *ctx);
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int (*flush_iso_completions)(struct fw_iso_context *ctx);
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int (*stop_iso)(struct fw_iso_context *ctx);
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};
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void fw_card_initialize(struct fw_card *card,
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const struct fw_card_driver *driver, struct device *device);
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int fw_card_add(struct fw_card *card, u32 max_receive, u32 link_speed, u64 guid,
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unsigned int supported_isoc_contexts);
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void fw_core_remove_card(struct fw_card *card);
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int fw_compute_block_crc(__be32 *block);
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void fw_schedule_bm_work(struct fw_card *card, unsigned long delay);
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/* -cdev */
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extern const struct file_operations fw_device_ops;
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void fw_device_cdev_update(struct fw_device *device);
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void fw_device_cdev_remove(struct fw_device *device);
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void fw_cdev_handle_phy_packet(struct fw_card *card, struct fw_packet *p);
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/* -device */
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extern struct rw_semaphore fw_device_rwsem;
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extern struct xarray fw_device_xa;
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extern int fw_cdev_major;
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static inline struct fw_device *fw_device_get(struct fw_device *device)
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{
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get_device(&device->device);
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return device;
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}
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static inline void fw_device_put(struct fw_device *device)
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{
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put_device(&device->device);
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}
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struct fw_device *fw_device_get_by_devt(dev_t devt);
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int fw_device_set_broadcast_channel(struct device *dev, void *gen);
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void fw_node_event(struct fw_card *card, struct fw_node *node, int event);
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/* -iso */
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int fw_iso_buffer_alloc(struct fw_iso_buffer *buffer, int page_count);
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int fw_iso_buffer_map_dma(struct fw_iso_buffer *buffer, struct fw_card *card,
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enum dma_data_direction direction);
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static inline void fw_iso_context_init_work(struct fw_iso_context *ctx, work_func_t func)
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{
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INIT_WORK(&ctx->work, func);
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}
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/* -topology */
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enum {
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FW_NODE_CREATED,
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FW_NODE_UPDATED,
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FW_NODE_DESTROYED,
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FW_NODE_LINK_ON,
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FW_NODE_LINK_OFF,
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FW_NODE_INITIATED_RESET,
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};
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struct fw_node {
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u16 node_id;
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u8 color;
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u8 port_count;
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u8 link_on:1;
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u8 initiated_reset:1;
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u8 b_path:1;
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u8 phy_speed:2; /* As in the self ID packet. */
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u8 max_speed:2; /* Minimum of all phy-speeds on the path from the
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* local node to this node. */
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u8 max_depth:4; /* Maximum depth to any leaf node */
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u8 max_hops:4; /* Max hops in this sub tree */
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struct kref kref;
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/* For serializing node topology into a list. */
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struct list_head link;
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/* Upper layer specific data. */
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void *data;
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struct fw_node *ports[] __counted_by(port_count);
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};
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static inline struct fw_node *fw_node_get(struct fw_node *node)
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{
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kref_get(&node->kref);
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return node;
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}
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static void release_node(struct kref *kref)
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{
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struct fw_node *node = container_of(kref, struct fw_node, kref);
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kfree(node);
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}
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static inline void fw_node_put(struct fw_node *node)
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{
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kref_put(&node->kref, release_node);
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}
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void fw_core_handle_bus_reset(struct fw_card *card, int node_id,
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int generation, int self_id_count, u32 *self_ids, bool bm_abdicate);
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void fw_destroy_nodes(struct fw_card *card);
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/*
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* Check whether new_generation is the immediate successor of old_generation.
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* Take counter roll-over at 255 (as per OHCI) into account.
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*/
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static inline bool is_next_generation(int new_generation, int old_generation)
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{
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return (new_generation & 0xff) == ((old_generation + 1) & 0xff);
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}
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/* -transaction */
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#define TCODE_LINK_INTERNAL 0xe
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static inline bool tcode_is_read_request(unsigned int tcode)
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{
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return (tcode & ~1u) == 4u;
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}
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static inline bool tcode_is_block_packet(unsigned int tcode)
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{
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return (tcode & 1u) != 0u;
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}
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static inline bool tcode_is_link_internal(unsigned int tcode)
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{
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return (tcode == TCODE_LINK_INTERNAL);
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}
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#define LOCAL_BUS 0xffc0
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/* OHCI-1394's default upper bound for physical DMA: 4 GB */
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#define FW_MAX_PHYSICAL_RANGE (1ULL << 32)
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void fw_core_handle_request(struct fw_card *card, struct fw_packet *request);
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void fw_core_handle_response(struct fw_card *card, struct fw_packet *packet);
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int fw_get_response_length(struct fw_request *request);
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void fw_fill_response(struct fw_packet *response, u32 *request_header,
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int rcode, void *payload, size_t length);
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void fw_request_get(struct fw_request *request);
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void fw_request_put(struct fw_request *request);
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// Convert the value of IEEE 1394 CYCLE_TIME register to the format of timeStamp field in
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// descriptors of 1394 OHCI.
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static inline u32 cycle_time_to_ohci_tstamp(u32 tstamp)
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{
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return (tstamp & 0x0ffff000) >> 12;
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}
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#define FW_PHY_CONFIG_NO_NODE_ID -1
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#define FW_PHY_CONFIG_CURRENT_GAP_COUNT -1
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void fw_send_phy_config(struct fw_card *card,
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int node_id, int generation, int gap_count);
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static inline bool is_ping_packet(u32 *data)
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{
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return (data[0] & 0xc0ffffff) == 0 && ~data[0] == data[1];
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}
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static inline bool is_in_fcp_region(u64 offset, size_t length)
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{
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return offset >= (CSR_REGISTER_BASE | CSR_FCP_COMMAND) &&
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offset + length <= (CSR_REGISTER_BASE | CSR_FCP_END);
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}
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#endif /* _FIREWIRE_CORE_H */
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