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The first few generations of TDX hardware have an erratum. Triggering
it in Linux requires some kind of kernel bug involving relatively exotic
memory writes to TDX private memory and will manifest via
spurious-looking machine checks when reading the affected memory.
Make an effort to detect these TDX-induced machine checks and spit out
a new blurb to dmesg so folks do not think their hardware is failing.
== Background ==
Virtually all kernel memory accesses operations happen in full
cachelines. In practice, writing a "byte" of memory usually reads a 64
byte cacheline of memory, modifies it, then writes the whole line back.
Those operations do not trigger this problem.
This problem is triggered by "partial" writes where a write transaction
of less than cacheline lands at the memory controller. The CPU does
these via non-temporal write instructions (like MOVNTI), or through
UC/WC memory mappings. The issue can also be triggered away from the
CPU by devices doing partial writes via DMA.
== Problem ==
A partial write to a TDX private memory cacheline will silently "poison"
the line. Subsequent reads will consume the poison and generate a
machine check. According to the TDX hardware spec, neither of these
things should have happened.
To add insult to injury, the Linux machine code will present these as a
literal "Hardware error" when they were, in fact, a software-triggered
issue.
== Solution ==
In the end, this issue is hard to trigger. Rather than do something
rash (and incomplete) like unmap TDX private memory from the direct map,
improve the machine check handler.
Currently, the #MC handler doesn't distinguish whether the memory is
TDX private memory or not but just dump, for instance, below message:
[...] mce: [Hardware Error]: CPU 147: Machine Check Exception: f Bank 1: bd80000000100134
[...] mce: [Hardware Error]: RIP 10:<ffffffffadb69870> {__tlb_remove_page_size+0x10/0xa0}
...
[...] mce: [Hardware Error]: Run the above through 'mcelog --ascii'
[...] mce: [Hardware Error]: Machine check: Data load in unrecoverable area of kernel
[...] Kernel panic - not syncing: Fatal local machine check
Which says "Hardware Error" and "Data load in unrecoverable area of
kernel".
Ideally, it's better for the log to say "software bug around TDX private
memory" instead of "Hardware Error". But in reality the real hardware
memory error can happen, and sadly such software-triggered #MC cannot be
distinguished from the real hardware error. Also, the error message is
used by userspace tool 'mcelog' to parse, so changing the output may
break userspace.
So keep the "Hardware Error". The "Data load in unrecoverable area of
kernel" is also helpful, so keep it too.
Instead of modifying above error log, improve the error log by printing
additional TDX related message to make the log like:
...
[...] mce: [Hardware Error]: Machine check: Data load in unrecoverable area of kernel
[...] mce: [Hardware Error]: Machine Check: TDX private memory error. Possible kernel bug.
Adding this additional message requires determination of whether the
memory page is TDX private memory. There is no existing infrastructure
to do that. Add an interface to query the TDX module to fill this gap.
== Impact ==
This issue requires some kind of kernel bug to trigger.
TDX private memory should never be mapped UC/WC. A partial write
originating from these mappings would require *two* bugs, first mapping
the wrong page, then writing the wrong memory. It would also be
detectable using traditional memory corruption techniques like
DEBUG_PAGEALLOC.
MOVNTI (and friends) could cause this issue with something like a simple
buffer overrun or use-after-free on the direct map. It should also be
detectable with normal debug techniques.
The one place where this might get nasty would be if the CPU read data
then wrote back the same data. That would trigger this problem but
would not, for instance, set off mechanisms like slab redzoning because
it doesn't actually corrupt data.
With an IOMMU at least, the DMA exposure is similar to the UC/WC issue.
TDX private memory would first need to be incorrectly mapped into the
I/O space and then a later DMA to that mapping would actually cause the
poisoning event.
[ dhansen: changelog tweaks ]
Signed-off-by: Kai Huang <kai.huang@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Reviewed-by: Yuan Yao <yuan.yao@intel.com>
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/all/20231208170740.53979-18-dave.hansen%40intel.com
128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021-2022 Intel Corporation */
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#ifndef _ASM_X86_TDX_H
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#define _ASM_X86_TDX_H
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#include <linux/init.h>
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#include <linux/bits.h>
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#include <asm/errno.h>
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#include <asm/ptrace.h>
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#include <asm/trapnr.h>
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#include <asm/shared/tdx.h>
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/*
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* SW-defined error codes.
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*
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* Bits 47:40 == 0xFF indicate Reserved status code class that never used by
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* TDX module.
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*/
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#define TDX_ERROR _BITUL(63)
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#define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40))
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#define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _UL(0xFFFF0000))
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#define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP)
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#define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD)
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/*
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* TDX module SEAMCALL leaf function error codes
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*/
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#define TDX_SUCCESS 0ULL
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#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL
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#ifndef __ASSEMBLY__
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#include <uapi/asm/mce.h>
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/*
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* Used by the #VE exception handler to gather the #VE exception
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* info from the TDX module. This is a software only structure
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* and not part of the TDX module/VMM ABI.
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*/
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struct ve_info {
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u64 exit_reason;
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u64 exit_qual;
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/* Guest Linear (virtual) Address */
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u64 gla;
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/* Guest Physical Address */
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u64 gpa;
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u32 instr_len;
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u32 instr_info;
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};
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#ifdef CONFIG_INTEL_TDX_GUEST
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void __init tdx_early_init(void);
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void tdx_get_ve_info(struct ve_info *ve);
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bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve);
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void tdx_safe_halt(void);
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bool tdx_early_handle_ve(struct pt_regs *regs);
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int tdx_mcall_get_report0(u8 *reportdata, u8 *tdreport);
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u64 tdx_hcall_get_quote(u8 *buf, size_t size);
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#else
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static inline void tdx_early_init(void) { };
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static inline void tdx_safe_halt(void) { };
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static inline bool tdx_early_handle_ve(struct pt_regs *regs) { return false; }
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#endif /* CONFIG_INTEL_TDX_GUEST */
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#if defined(CONFIG_KVM_GUEST) && defined(CONFIG_INTEL_TDX_GUEST)
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long tdx_kvm_hypercall(unsigned int nr, unsigned long p1, unsigned long p2,
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unsigned long p3, unsigned long p4);
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#else
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static inline long tdx_kvm_hypercall(unsigned int nr, unsigned long p1,
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unsigned long p2, unsigned long p3,
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unsigned long p4)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_INTEL_TDX_GUEST && CONFIG_KVM_GUEST */
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#ifdef CONFIG_INTEL_TDX_HOST
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u64 __seamcall(u64 fn, struct tdx_module_args *args);
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u64 __seamcall_ret(u64 fn, struct tdx_module_args *args);
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u64 __seamcall_saved_ret(u64 fn, struct tdx_module_args *args);
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void tdx_init(void);
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#include <asm/archrandom.h>
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typedef u64 (*sc_func_t)(u64 fn, struct tdx_module_args *args);
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static inline u64 sc_retry(sc_func_t func, u64 fn,
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struct tdx_module_args *args)
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{
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int retry = RDRAND_RETRY_LOOPS;
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u64 ret;
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do {
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ret = func(fn, args);
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} while (ret == TDX_RND_NO_ENTROPY && --retry);
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return ret;
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}
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#define seamcall(_fn, _args) sc_retry(__seamcall, (_fn), (_args))
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#define seamcall_ret(_fn, _args) sc_retry(__seamcall_ret, (_fn), (_args))
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#define seamcall_saved_ret(_fn, _args) sc_retry(__seamcall_saved_ret, (_fn), (_args))
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int tdx_cpu_enable(void);
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int tdx_enable(void);
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const char *tdx_dump_mce_info(struct mce *m);
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#else
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static inline void tdx_init(void) { }
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static inline int tdx_cpu_enable(void) { return -ENODEV; }
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static inline int tdx_enable(void) { return -ENODEV; }
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static inline const char *tdx_dump_mce_info(struct mce *m) { return NULL; }
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#endif /* CONFIG_INTEL_TDX_HOST */
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_X86_TDX_H */
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