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Intel Advanced Performance Extensions (APX) extends the EVEX prefix to support: - extended general purpose registers (EGPRs) i.e. r16 to r31 - Push-Pop Acceleration (PPX) hints - new data destination (NDD) register - suppress status flags writes (NF) of common instructions - new instructions Refer to the Intel Advanced Performance Extensions (Intel APX) Architecture Specification for details. The extended EVEX prefix does not need amended instruction decoder logic, except in one area. Some instructions are defined as SCALABLE which means the EVEX.W bit and EVEX.pp bits are used to determine operand size. Specifically, if an instruction is SCALABLE and EVEX.W is zero, then EVEX.pp value 0 (representing no prefix NP) means default operand size, whereas EVEX.pp value 1 (representing 66 prefix) means operand size override i.e. 16 bits Add an attribute (INAT_EVEX_SCALABLE) to identify such instructions, and amend the logic appropriately. Amend the awk script that generates the attribute tables from the opcode map, to recognise "(es)" as attribute INAT_EVEX_SCALABLE. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240502105853.5338-8-adrian.hunter@intel.com
246 lines
6.4 KiB
C
246 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_X86_INAT_H
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#define _ASM_X86_INAT_H
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/*
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* x86 instruction attributes
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*
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* Written by Masami Hiramatsu <mhiramat@redhat.com>
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*/
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#include <asm/inat_types.h> /* __ignore_sync_check__ */
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/*
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* Internal bits. Don't use bitmasks directly, because these bits are
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* unstable. You should use checking functions.
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*/
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#define INAT_OPCODE_TABLE_SIZE 256
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#define INAT_GROUP_TABLE_SIZE 8
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/* Legacy last prefixes */
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#define INAT_PFX_OPNDSZ 1 /* 0x66 */ /* LPFX1 */
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#define INAT_PFX_REPE 2 /* 0xF3 */ /* LPFX2 */
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#define INAT_PFX_REPNE 3 /* 0xF2 */ /* LPFX3 */
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/* Other Legacy prefixes */
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#define INAT_PFX_LOCK 4 /* 0xF0 */
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#define INAT_PFX_CS 5 /* 0x2E */
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#define INAT_PFX_DS 6 /* 0x3E */
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#define INAT_PFX_ES 7 /* 0x26 */
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#define INAT_PFX_FS 8 /* 0x64 */
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#define INAT_PFX_GS 9 /* 0x65 */
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#define INAT_PFX_SS 10 /* 0x36 */
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#define INAT_PFX_ADDRSZ 11 /* 0x67 */
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/* x86-64 REX prefix */
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#define INAT_PFX_REX 12 /* 0x4X */
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/* AVX VEX prefixes */
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#define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */
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#define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */
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#define INAT_PFX_EVEX 15 /* EVEX prefix */
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/* x86-64 REX2 prefix */
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#define INAT_PFX_REX2 16 /* 0xD5 */
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#define INAT_LSTPFX_MAX 3
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#define INAT_LGCPFX_MAX 11
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/* Immediate size */
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#define INAT_IMM_BYTE 1
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#define INAT_IMM_WORD 2
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#define INAT_IMM_DWORD 3
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#define INAT_IMM_QWORD 4
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#define INAT_IMM_PTR 5
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#define INAT_IMM_VWORD32 6
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#define INAT_IMM_VWORD 7
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/* Legacy prefix */
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#define INAT_PFX_OFFS 0
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#define INAT_PFX_BITS 5
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#define INAT_PFX_MAX ((1 << INAT_PFX_BITS) - 1)
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#define INAT_PFX_MASK (INAT_PFX_MAX << INAT_PFX_OFFS)
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/* Escape opcodes */
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#define INAT_ESC_OFFS (INAT_PFX_OFFS + INAT_PFX_BITS)
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#define INAT_ESC_BITS 2
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#define INAT_ESC_MAX ((1 << INAT_ESC_BITS) - 1)
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#define INAT_ESC_MASK (INAT_ESC_MAX << INAT_ESC_OFFS)
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/* Group opcodes (1-16) */
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#define INAT_GRP_OFFS (INAT_ESC_OFFS + INAT_ESC_BITS)
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#define INAT_GRP_BITS 5
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#define INAT_GRP_MAX ((1 << INAT_GRP_BITS) - 1)
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#define INAT_GRP_MASK (INAT_GRP_MAX << INAT_GRP_OFFS)
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/* Immediates */
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#define INAT_IMM_OFFS (INAT_GRP_OFFS + INAT_GRP_BITS)
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#define INAT_IMM_BITS 3
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#define INAT_IMM_MASK (((1 << INAT_IMM_BITS) - 1) << INAT_IMM_OFFS)
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/* Flags */
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#define INAT_FLAG_OFFS (INAT_IMM_OFFS + INAT_IMM_BITS)
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#define INAT_MODRM (1 << (INAT_FLAG_OFFS))
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#define INAT_FORCE64 (1 << (INAT_FLAG_OFFS + 1))
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#define INAT_SCNDIMM (1 << (INAT_FLAG_OFFS + 2))
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#define INAT_MOFFSET (1 << (INAT_FLAG_OFFS + 3))
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#define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4))
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#define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5))
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#define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6))
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#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7))
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#define INAT_NO_REX2 (1 << (INAT_FLAG_OFFS + 8))
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#define INAT_REX2_VARIANT (1 << (INAT_FLAG_OFFS + 9))
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#define INAT_EVEX_SCALABLE (1 << (INAT_FLAG_OFFS + 10))
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/* Attribute making macros for attribute tables */
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#define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS)
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#define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS)
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#define INAT_MAKE_GROUP(grp) ((grp << INAT_GRP_OFFS) | INAT_MODRM)
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#define INAT_MAKE_IMM(imm) (imm << INAT_IMM_OFFS)
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/* Identifiers for segment registers */
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#define INAT_SEG_REG_IGNORE 0
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#define INAT_SEG_REG_DEFAULT 1
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#define INAT_SEG_REG_CS 2
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#define INAT_SEG_REG_SS 3
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#define INAT_SEG_REG_DS 4
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#define INAT_SEG_REG_ES 5
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#define INAT_SEG_REG_FS 6
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#define INAT_SEG_REG_GS 7
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/* Attribute search APIs */
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extern insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode);
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extern int inat_get_last_prefix_id(insn_byte_t last_pfx);
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extern insn_attr_t inat_get_escape_attribute(insn_byte_t opcode,
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int lpfx_id,
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insn_attr_t esc_attr);
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extern insn_attr_t inat_get_group_attribute(insn_byte_t modrm,
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int lpfx_id,
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insn_attr_t esc_attr);
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extern insn_attr_t inat_get_avx_attribute(insn_byte_t opcode,
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insn_byte_t vex_m,
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insn_byte_t vex_pp);
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/* Attribute checking functions */
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static inline int inat_is_legacy_prefix(insn_attr_t attr)
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{
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attr &= INAT_PFX_MASK;
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return attr && attr <= INAT_LGCPFX_MAX;
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}
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static inline int inat_is_address_size_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_ADDRSZ;
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}
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static inline int inat_is_operand_size_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_OPNDSZ;
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}
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static inline int inat_is_rex_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_REX;
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}
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static inline int inat_is_rex2_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_REX2;
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}
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static inline int inat_last_prefix_id(insn_attr_t attr)
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{
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if ((attr & INAT_PFX_MASK) > INAT_LSTPFX_MAX)
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return 0;
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else
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return attr & INAT_PFX_MASK;
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}
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static inline int inat_is_vex_prefix(insn_attr_t attr)
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{
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attr &= INAT_PFX_MASK;
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return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 ||
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attr == INAT_PFX_EVEX;
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}
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static inline int inat_is_evex_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX;
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}
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static inline int inat_is_vex3_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_VEX3;
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}
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static inline int inat_is_escape(insn_attr_t attr)
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{
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return attr & INAT_ESC_MASK;
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}
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static inline int inat_escape_id(insn_attr_t attr)
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{
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return (attr & INAT_ESC_MASK) >> INAT_ESC_OFFS;
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}
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static inline int inat_is_group(insn_attr_t attr)
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{
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return attr & INAT_GRP_MASK;
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}
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static inline int inat_group_id(insn_attr_t attr)
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{
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return (attr & INAT_GRP_MASK) >> INAT_GRP_OFFS;
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}
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static inline int inat_group_common_attribute(insn_attr_t attr)
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{
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return attr & ~INAT_GRP_MASK;
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}
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static inline int inat_has_immediate(insn_attr_t attr)
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{
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return attr & INAT_IMM_MASK;
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}
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static inline int inat_immediate_size(insn_attr_t attr)
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{
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return (attr & INAT_IMM_MASK) >> INAT_IMM_OFFS;
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}
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static inline int inat_has_modrm(insn_attr_t attr)
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{
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return attr & INAT_MODRM;
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}
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static inline int inat_is_force64(insn_attr_t attr)
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{
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return attr & INAT_FORCE64;
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}
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static inline int inat_has_second_immediate(insn_attr_t attr)
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{
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return attr & INAT_SCNDIMM;
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}
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static inline int inat_has_moffset(insn_attr_t attr)
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{
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return attr & INAT_MOFFSET;
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}
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static inline int inat_has_variant(insn_attr_t attr)
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{
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return attr & INAT_VARIANT;
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}
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static inline int inat_accept_vex(insn_attr_t attr)
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{
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return attr & INAT_VEXOK;
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}
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static inline int inat_must_vex(insn_attr_t attr)
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{
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return attr & (INAT_VEXONLY | INAT_EVEXONLY);
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}
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static inline int inat_must_evex(insn_attr_t attr)
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{
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return attr & INAT_EVEXONLY;
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}
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static inline int inat_evex_scalable(insn_attr_t attr)
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{
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return attr & INAT_EVEX_SCALABLE;
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}
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#endif
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