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128b0c9781
David and a few others reported that on certain newer systems some legacy
interrupts fail to work correctly.
Debugging revealed that the BIOS of these systems leaves the legacy PIC in
uninitialized state which makes the PIC detection fail and the kernel
switches to a dummy implementation.
Unfortunately this fallback causes quite some code to fail as it depends on
checks for the number of legacy PIC interrupts or the availability of the
real PIC.
In theory there is no reason to use the PIC on any modern system when
IO/APIC is available, but the dependencies on the related checks cannot be
resolved trivially and on short notice. This needs lots of analysis and
rework.
The PIC detection has been added to avoid quirky checks and force selection
of the dummy implementation all over the place, especially in VM guest
scenarios. So it's not an option to revert the relevant commit as that
would break a lot of other scenarios.
One solution would be to try to initialize the PIC on detection fail and
retry the detection, but that puts the burden on everything which does not
have a PIC.
Fortunately the ACPI/MADT table header has a flag field, which advertises
in bit 0 that the system is PCAT compatible, which means it has a legacy
8259 PIC.
Evaluate that bit and if set avoid the detection routine and keep the real
PIC installed, which then gets initialized (for nothing) and makes the rest
of the code with all the dependencies work again.
Fixes: e179f69141 ("x86, irq, pic: Probe for legacy PIC and set legacy_pic appropriately")
Reported-by: David Lazar <dlazar@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: David Lazar <dlazar@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Cc: stable@vger.kernel.org
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218003
Link: https://lore.kernel.org/r/875y2u5s8g.ffs@tglx
88 lines
2.0 KiB
C
88 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_I8259_H
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#define _ASM_X86_I8259_H
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#include <linux/delay.h>
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#include <asm/io.h>
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extern unsigned int cached_irq_mask;
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#define __byte(x, y) (((unsigned char *)&(y))[x])
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#define cached_master_mask (__byte(0, cached_irq_mask))
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#define cached_slave_mask (__byte(1, cached_irq_mask))
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/* i8259A PIC registers */
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#define PIC_MASTER_CMD 0x20
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#define PIC_MASTER_IMR 0x21
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#define PIC_MASTER_ISR PIC_MASTER_CMD
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#define PIC_MASTER_POLL PIC_MASTER_ISR
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#define PIC_MASTER_OCW3 PIC_MASTER_ISR
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#define PIC_SLAVE_CMD 0xa0
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#define PIC_SLAVE_IMR 0xa1
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#define PIC_ELCR1 0x4d0
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#define PIC_ELCR2 0x4d1
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/* i8259A PIC related value */
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#define PIC_CASCADE_IR 2
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#define MASTER_ICW4_DEFAULT 0x01
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#define SLAVE_ICW4_DEFAULT 0x01
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#define PIC_ICW4_AEOI 2
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extern raw_spinlock_t i8259A_lock;
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/* the PIC may need a careful delay on some platforms, hence specific calls */
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static inline unsigned char inb_pic(unsigned int port)
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{
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unsigned char value = inb(port);
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/*
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* delay for some accesses to PIC on motherboard or in chipset
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* must be at least one microsecond, so be safe here:
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*/
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udelay(2);
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return value;
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}
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static inline void outb_pic(unsigned char value, unsigned int port)
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{
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outb(value, port);
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/*
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* delay for some accesses to PIC on motherboard or in chipset
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* must be at least one microsecond, so be safe here:
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*/
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udelay(2);
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}
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extern struct irq_chip i8259A_chip;
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struct legacy_pic {
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int nr_legacy_irqs;
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struct irq_chip *chip;
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void (*mask)(unsigned int irq);
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void (*unmask)(unsigned int irq);
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void (*mask_all)(void);
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void (*restore_mask)(void);
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void (*init)(int auto_eoi);
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int (*probe)(void);
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int (*irq_pending)(unsigned int irq);
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void (*make_irq)(unsigned int irq);
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};
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void legacy_pic_pcat_compat(void);
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extern struct legacy_pic *legacy_pic;
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extern struct legacy_pic null_legacy_pic;
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static inline bool has_legacy_pic(void)
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{
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return legacy_pic != &null_legacy_pic;
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}
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static inline int nr_legacy_irqs(void)
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{
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return legacy_pic->nr_legacy_irqs;
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}
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#endif /* _ASM_X86_I8259_H */
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