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946bb33d33
The cache ops are also used by the pmem code which is unconditionally
built into the kernel. Move them into a separate file that is built
based on the correct config option.
Fixes: fd96278127 ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> #
Link: https://lore.kernel.org/r/20231028155101.1039049-1-hch@lst.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
18 lines
419 B
C
18 lines
419 B
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*/
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#include <asm/dma-noncoherent.h>
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struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init;
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void
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riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops)
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{
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if (!ops)
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return;
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noncoherent_cache_ops = *ops;
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}
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EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops);
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