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1a736d98c8
This reverts commitbccc58986a. When STRICT_KERNEL_RWX is selected, EXEC memory must stop where RW memory start. When pinning iTLBs it means an 8M alignment for RW data start. That may be acceptable on boards with a lot of memory but one of my supported boards only has 32 Mbytes and this forced alignment leads to a waste of almost 4 Mbytes with is more than 10% of the total memory. So revert commitbccc58986a("powerpc/8xx: Always pin kernel text TLB") but don't restore previous behaviour in ITLB miss handler as now kernel PGD entries are copied into each process PGDIR. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/01b6780b860c8043b51a1ba9d83acfc6f2dde910.1724173828.git.christophe.leroy@csgroup.eu
208 lines
4.8 KiB
Plaintext
208 lines
4.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CPM1
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bool
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select CPM
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choice
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prompt "8xx Machine Type"
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depends on PPC_8xx
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default MPC885ADS
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config MPC8XXFADS
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bool "FADS"
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config MPC86XADS
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bool "MPC86XADS"
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select CPM1
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help
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MPC86x Application Development System by Freescale Semiconductor.
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The MPC86xADS is meant to serve as a platform for s/w and h/w
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development around the MPC86X processor families.
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config MPC885ADS
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bool "MPC885ADS"
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select CPM1
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select OF_DYNAMIC
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help
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Freescale Semiconductor MPC885 Application Development System (ADS).
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Also known as DUET.
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The MPC885ADS is meant to serve as a platform for s/w and h/w
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development around the MPC885 processor family.
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config PPC_EP88XC
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bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
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select CPM1
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help
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This enables support for the Embedded Planet EP88xC board.
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This board is also resold by Freescale as the QUICCStart
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MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
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config PPC_ADDER875
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bool "Analogue & Micro Adder 875"
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select CPM1
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help
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This enables support for the Analogue & Micro Adder 875
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board.
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config TQM8XX
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bool "TQM8XX"
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select CPM1
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help
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support for the mpc8xx based boards from TQM.
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endchoice
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menu "Freescale Ethernet driver platform-specific options"
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depends on (FS_ENET && MPC885ADS)
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config MPC8xx_SECOND_ETH
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bool "Second Ethernet channel"
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depends on MPC885ADS
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default y
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help
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This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
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The latter will use SCC1, for 885ADS you can select it below.
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choice
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prompt "Second Ethernet channel"
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depends on MPC8xx_SECOND_ETH
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default MPC8xx_SECOND_ETH_FEC2
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config MPC8xx_SECOND_ETH_FEC2
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bool "FEC2"
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depends on MPC885ADS
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help
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Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
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(often 2-nd UART) will not work if this is enabled.
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config MPC8xx_SECOND_ETH_SCC3
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bool "SCC3"
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depends on MPC885ADS
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help
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Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
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(often 1-nd UART) will not work if this is enabled.
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endchoice
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endmenu
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#
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# MPC8xx Communication options
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#
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menu "MPC8xx CPM Options"
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depends on PPC_8xx
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# This doesn't really belong here, but it is convenient to ask
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# 8xx specific questions.
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comment "Generic MPC8xx Options"
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config 8xx_GPIO
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bool "GPIO API Support"
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select GPIOLIB
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select OF_GPIO_MM_GPIOCHIP
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help
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Saying Y here will cause the ports on an MPC8xx processor to be used
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with the GPIO API. If you say N here, the kernel needs less memory.
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If in doubt, say Y here.
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config 8xx_CPU15
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bool "CPU15 Silicon Errata"
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depends on !HUGETLB_PAGE
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default y
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help
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This enables a workaround for erratum CPU15 on MPC8xx chips.
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This bug can cause incorrect code execution under certain
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circumstances. This workaround adds some overhead (a TLB miss
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every time execution crosses a page boundary), and you may wish
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to disable it if you have worked around the bug in the compiler
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(by not placing conditional branches or branches to LR or CTR
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in the last word of a page, with a target of the last cache
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line in the next page), or if you have used some other
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workaround.
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If in doubt, say Y here.
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choice
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prompt "Microcode patch selection"
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default NO_UCODE_PATCH
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help
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Help not implemented yet, coming soon.
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config NO_UCODE_PATCH
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bool "None"
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config USB_SOF_UCODE_PATCH
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bool "USB SOF patch"
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help
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Help not implemented yet, coming soon.
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config I2C_SPI_UCODE_PATCH
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bool "I2C/SPI relocation patch"
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help
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Help not implemented yet, coming soon.
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config I2C_SPI_SMC1_UCODE_PATCH
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bool "I2C/SPI/SMC1 relocation patch"
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help
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Help not implemented yet, coming soon.
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config SMC_UCODE_PATCH
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bool "SMC relocation patch"
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help
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This microcode relocates SMC1 and SMC2 parameter RAMs at
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offset 0x1ec0 and 0x1fc0 to allow extended parameter RAM
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for SCC3 and SCC4.
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endchoice
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config UCODE_PATCH
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bool
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default y
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depends on !NO_UCODE_PATCH
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menu "8xx advanced setup"
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depends on PPC_8xx
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config PIN_TLB
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bool "Pinned Kernel TLBs"
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depends on ADVANCED_OPTIONS
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help
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On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
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table 4 TLBs can be pinned.
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It reduces the amount of usable TLBs to 28 (ie by 12%). That's the
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reason why we make it selectable.
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This option does nothing, it just activate the selection of what
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to pin.
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config PIN_TLB_DATA
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bool "Pinned TLB for DATA"
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depends on PIN_TLB
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default y
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help
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This pins the first 32 Mbytes of memory with 8M pages.
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config PIN_TLB_IMMR
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bool "Pinned TLB for IMMR"
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depends on PIN_TLB
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default y
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help
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This pins the IMMR area with a 512kbytes page. In case
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CONFIG_PIN_TLB_DATA is also selected, it will reduce
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CONFIG_PIN_TLB_DATA to 24 Mbytes.
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config PIN_TLB_TEXT
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bool "Pinned TLB for TEXT"
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depends on PIN_TLB
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default y
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help
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This pins kernel text with 8M pages.
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endmenu
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endmenu
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