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b6405f0829
When patching the kernel code some alternatives depend on SMP vs. !SMP. Use the value of num_present_cpus() instead of num_online_cpus() to decide, otherwise we may run into issues if and additional CPU is enabled after having loaded a module while only one CPU was enabled. Signed-off-by: Helge Deller <deller@gmx.de> Cc: <stable@vger.kernel.org> # v6.1+
123 lines
3.3 KiB
C
123 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Alternative live-patching for parisc.
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* Copyright (C) 2018 Helge Deller <deller@gmx.de>
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*
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*/
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/alternative.h>
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#include <asm/cacheflush.h>
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#include <linux/module.h>
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static int no_alternatives;
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static int __init setup_no_alternatives(char *str)
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{
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no_alternatives = 1;
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return 1;
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}
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__setup("no-alternatives", setup_no_alternatives);
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void __init_or_module apply_alternatives(struct alt_instr *start,
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struct alt_instr *end, const char *module_name)
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{
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struct alt_instr *entry;
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int index = 0, applied = 0;
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int num_cpus = num_present_cpus();
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u16 cond_check;
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cond_check = ALT_COND_ALWAYS |
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((num_cpus == 1) ? ALT_COND_NO_SMP : 0) |
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((cache_info.dc_size == 0) ? ALT_COND_NO_DCACHE : 0) |
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((cache_info.ic_size == 0) ? ALT_COND_NO_ICACHE : 0) |
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(running_on_qemu ? ALT_COND_RUN_ON_QEMU : 0) |
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((split_tlb == 0) ? ALT_COND_NO_SPLIT_TLB : 0) |
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/*
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* If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit
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* set (bit #61, big endian), we have to flush and sync every
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* time IO-PDIR is changed in Ike/Astro.
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*/
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(((boot_cpu_data.cpu_type > pcxw_) &&
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((boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) == 0))
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? ALT_COND_NO_IOC_FDC : 0);
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for (entry = start; entry < end; entry++, index++) {
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u32 *from, replacement;
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u16 cond;
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s16 len;
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from = (u32 *)((ulong)&entry->orig_offset + entry->orig_offset);
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len = entry->len;
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cond = entry->cond;
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replacement = entry->replacement;
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WARN_ON(!cond);
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if ((cond & ALT_COND_ALWAYS) == 0 && no_alternatives)
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continue;
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pr_debug("Check %d: Cond 0x%x, Replace %02d instructions @ 0x%px with 0x%08x\n",
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index, cond, len, from, replacement);
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/* Bounce out if none of the conditions are true. */
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if ((cond & cond_check) == 0)
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continue;
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/* Want to replace pdtlb by a pdtlb,l instruction? */
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if (replacement == INSN_PxTLB) {
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replacement = *from;
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if (boot_cpu_data.cpu_type >= pcxu) /* >= pa2.0 ? */
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replacement |= (1 << 10); /* set el bit */
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}
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/*
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* Replace instruction with NOPs?
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* For long distance insert a branch instruction instead.
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*/
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if (replacement == INSN_NOP && len > 1)
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replacement = 0xe8000002 + (len-2)*8; /* "b,n .+8" */
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pr_debug("ALTERNATIVE %3d: Cond %2x, Replace %2d instructions to 0x%08x @ 0x%px (%pS)\n",
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index, cond, len, replacement, from, from);
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if (len < 0) {
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/* Replace multiple instruction by new code */
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u32 *source;
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len = -len;
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source = (u32 *)((ulong)&entry->replacement + entry->replacement);
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memcpy(from, source, 4 * len);
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} else {
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/* Replace by one instruction */
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*from = replacement;
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}
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applied++;
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}
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pr_info("%s%salternatives: applied %d out of %d patches\n",
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module_name ? : "", module_name ? " " : "",
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applied, index);
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}
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void __init apply_alternatives_all(void)
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{
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set_kernel_text_rw(1);
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apply_alternatives((struct alt_instr *) &__alt_instructions,
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(struct alt_instr *) &__alt_instructions_end, NULL);
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if (cache_info.dc_size == 0 && cache_info.ic_size == 0) {
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pr_info("alternatives: optimizing cache-flushes.\n");
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static_branch_disable(&parisc_has_cache);
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}
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if (cache_info.dc_size == 0)
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static_branch_disable(&parisc_has_dcache);
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if (cache_info.ic_size == 0)
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static_branch_disable(&parisc_has_icache);
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set_kernel_text_rw(0);
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}
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