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75ded18a5e
Add LSX and LASX implementations of xor operations, operating on 64 bytes (one L1 cache line) at a time, for a balance between memory utilization and instruction mix. Huacai confirmed that all future LoongArch implementations by Loongson (that we care) will likely also feature 64-byte cache lines, and experiments show no throughput improvement with further unrolling. Performance numbers measured during system boot on a 3A5000 @ 2.5GHz: > 8regs : 12702 MB/sec > 8regs_prefetch : 10920 MB/sec > 32regs : 12686 MB/sec > 32regs_prefetch : 10918 MB/sec > lsx : 17589 MB/sec > lasx : 26116 MB/sec Acked-by: Song Liu <song@kernel.org> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2023 WANG Xuerui <git@xen0n.name>
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*
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* Template for XOR operations, instantiated in xor_simd.c.
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*
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* Expected preprocessor definitions:
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*
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* - LINE_WIDTH
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* - XOR_FUNC_NAME(nr)
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* - LD_INOUT_LINE(buf)
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* - LD_AND_XOR_LINE(buf)
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* - ST_LINE(buf)
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*/
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void XOR_FUNC_NAME(2)(unsigned long bytes,
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unsigned long * __restrict v1,
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const unsigned long * __restrict v2)
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{
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unsigned long lines = bytes / LINE_WIDTH;
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do {
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__asm__ __volatile__ (
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LD_INOUT_LINE(v1)
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LD_AND_XOR_LINE(v2)
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ST_LINE(v1)
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: : [v1] "r"(v1), [v2] "r"(v2) : "memory"
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);
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v1 += LINE_WIDTH / sizeof(unsigned long);
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v2 += LINE_WIDTH / sizeof(unsigned long);
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} while (--lines > 0);
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}
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void XOR_FUNC_NAME(3)(unsigned long bytes,
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unsigned long * __restrict v1,
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const unsigned long * __restrict v2,
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const unsigned long * __restrict v3)
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{
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unsigned long lines = bytes / LINE_WIDTH;
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do {
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__asm__ __volatile__ (
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LD_INOUT_LINE(v1)
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LD_AND_XOR_LINE(v2)
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LD_AND_XOR_LINE(v3)
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ST_LINE(v1)
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: : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3) : "memory"
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);
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v1 += LINE_WIDTH / sizeof(unsigned long);
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v2 += LINE_WIDTH / sizeof(unsigned long);
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v3 += LINE_WIDTH / sizeof(unsigned long);
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} while (--lines > 0);
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}
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void XOR_FUNC_NAME(4)(unsigned long bytes,
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unsigned long * __restrict v1,
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const unsigned long * __restrict v2,
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const unsigned long * __restrict v3,
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const unsigned long * __restrict v4)
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{
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unsigned long lines = bytes / LINE_WIDTH;
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do {
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__asm__ __volatile__ (
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LD_INOUT_LINE(v1)
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LD_AND_XOR_LINE(v2)
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LD_AND_XOR_LINE(v3)
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LD_AND_XOR_LINE(v4)
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ST_LINE(v1)
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: : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3), [v4] "r"(v4)
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: "memory"
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);
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v1 += LINE_WIDTH / sizeof(unsigned long);
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v2 += LINE_WIDTH / sizeof(unsigned long);
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v3 += LINE_WIDTH / sizeof(unsigned long);
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v4 += LINE_WIDTH / sizeof(unsigned long);
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} while (--lines > 0);
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}
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void XOR_FUNC_NAME(5)(unsigned long bytes,
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unsigned long * __restrict v1,
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const unsigned long * __restrict v2,
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const unsigned long * __restrict v3,
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const unsigned long * __restrict v4,
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const unsigned long * __restrict v5)
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{
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unsigned long lines = bytes / LINE_WIDTH;
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do {
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__asm__ __volatile__ (
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LD_INOUT_LINE(v1)
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LD_AND_XOR_LINE(v2)
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LD_AND_XOR_LINE(v3)
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LD_AND_XOR_LINE(v4)
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LD_AND_XOR_LINE(v5)
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ST_LINE(v1)
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: : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3), [v4] "r"(v4),
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[v5] "r"(v5) : "memory"
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);
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v1 += LINE_WIDTH / sizeof(unsigned long);
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v2 += LINE_WIDTH / sizeof(unsigned long);
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v3 += LINE_WIDTH / sizeof(unsigned long);
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v4 += LINE_WIDTH / sizeof(unsigned long);
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v5 += LINE_WIDTH / sizeof(unsigned long);
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} while (--lines > 0);
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}
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