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Counter updates for 6.11
Primarily consists of cleanups and updates for ti-eqep; ti-eqep now supports over/underflow events and can be build for K3 devices. In addition, ftm-quaddec is updated to add a missing MODULE_DESCRIPTION() macro. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCZoPFuAAKCRC1SFbKvhIj K/wdAQCTcrXue1ORBUP/8og6LFWyOgHn653vb3pG070Bqtk4MgEA+VijD3DWp0XA pFLHTZhIZil7Y+SaFu2WfF+g1mViNQI= =CmY2 -----END PGP SIGNATURE----- Merge tag 'counter-updates-for-6.11' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-next William writes: Counter updates for 6.11 Primarily consists of cleanups and updates for ti-eqep; ti-eqep now supports over/underflow events and can be build for K3 devices. In addition, ftm-quaddec is updated to add a missing MODULE_DESCRIPTION() macro. * tag 'counter-updates-for-6.11' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: ti-eqep: Allow eQEP driver to be built for K3 devices counter/ti-eqep: Add new ti-am62-eqep compatible dt-bindings: counter: Add new ti,am62-eqep compatible counter: ti-eqep: remove counter_priv() wrapper counter: ti-eqep: remove unused struct member counter: ti-eqep: implement over/underflow events counter: ftm-quaddec: add missing MODULE_DESCRIPTION() macro
This commit is contained in:
Greg Kroah-Hartman
commit
7254a298cf
@ -11,7 +11,9 @@ maintainers:
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properties:
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compatible:
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const: ti,am3352-eqep
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enum:
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- ti,am3352-eqep
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- ti,am62-eqep
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reg:
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maxItems: 1
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@ -21,19 +23,35 @@ properties:
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maxItems: 1
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clocks:
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description: The clock that determines the SYSCLKOUT rate for the eQEP
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peripheral.
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description: The functional and interface clock that determines the clock
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rate for the eQEP peripheral.
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maxItems: 1
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clock-names:
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const: sysclkout
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power-domains:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ti,am62-eqep
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then:
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properties:
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clock-names: false
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required:
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- power-domains
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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@ -43,7 +61,6 @@ examples:
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compatible = "ti,am3352-eqep";
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reg = <0x180 0x80>;
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clocks = <&l4ls_gclk>;
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clock-names = "sysclkout";
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interrupts = <79>;
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};
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@ -138,7 +138,7 @@ config TI_ECAP_CAPTURE
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config TI_EQEP
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tristate "TI eQEP counter driver"
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depends on (SOC_AM33XX || COMPILE_TEST)
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depends on SOC_AM33XX || ARCH_K3 || COMPILE_TEST
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select REGMAP_MMIO
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help
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Select this option to enable the Texas Instruments Enhanced Quadrature
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@ -322,6 +322,7 @@ static struct platform_driver ftm_quaddec_driver = {
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module_platform_driver(ftm_quaddec_driver);
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MODULE_DESCRIPTION("Flex Timer Module Quadrature decoder");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Kjeld Flarup <kfa@deif.com>");
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MODULE_AUTHOR("Patrick Havelange <patrick.havelange@essensium.com>");
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@ -8,6 +8,7 @@
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/counter.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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@ -68,6 +69,44 @@
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#define QEPCTL_UTE BIT(1)
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#define QEPCTL_WDE BIT(0)
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#define QEINT_UTO BIT(11)
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#define QEINT_IEL BIT(10)
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#define QEINT_SEL BIT(9)
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#define QEINT_PCM BIT(8)
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#define QEINT_PCR BIT(7)
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#define QEINT_PCO BIT(6)
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#define QEINT_PCU BIT(5)
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#define QEINT_WTO BIT(4)
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#define QEINT_QDC BIT(3)
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#define QEINT_PHE BIT(2)
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#define QEINT_PCE BIT(1)
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#define QFLG_UTO BIT(11)
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#define QFLG_IEL BIT(10)
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#define QFLG_SEL BIT(9)
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#define QFLG_PCM BIT(8)
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#define QFLG_PCR BIT(7)
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#define QFLG_PCO BIT(6)
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#define QFLG_PCU BIT(5)
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#define QFLG_WTO BIT(4)
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#define QFLG_QDC BIT(3)
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#define QFLG_PHE BIT(2)
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#define QFLG_PCE BIT(1)
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#define QFLG_INT BIT(0)
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#define QCLR_UTO BIT(11)
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#define QCLR_IEL BIT(10)
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#define QCLR_SEL BIT(9)
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#define QCLR_PCM BIT(8)
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#define QCLR_PCR BIT(7)
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#define QCLR_PCO BIT(6)
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#define QCLR_PCU BIT(5)
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#define QCLR_WTO BIT(4)
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#define QCLR_QDC BIT(3)
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#define QCLR_PHE BIT(2)
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#define QCLR_PCE BIT(1)
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#define QCLR_INT BIT(0)
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/* EQEP Inputs */
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enum {
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TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
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@ -83,20 +122,14 @@ enum ti_eqep_count_func {
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};
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struct ti_eqep_cnt {
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struct counter_device counter;
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struct regmap *regmap32;
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struct regmap *regmap16;
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};
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static struct ti_eqep_cnt *ti_eqep_count_from_counter(struct counter_device *counter)
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{
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return counter_priv(counter);
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}
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static int ti_eqep_count_read(struct counter_device *counter,
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struct counter_count *count, u64 *val)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 cnt;
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regmap_read(priv->regmap32, QPOSCNT, &cnt);
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@ -108,7 +141,7 @@ static int ti_eqep_count_read(struct counter_device *counter,
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static int ti_eqep_count_write(struct counter_device *counter,
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struct counter_count *count, u64 val)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 max;
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regmap_read(priv->regmap32, QPOSMAX, &max);
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@ -122,7 +155,7 @@ static int ti_eqep_function_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function *function)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 qdecctl;
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regmap_read(priv->regmap16, QDECCTL, &qdecctl);
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@ -149,7 +182,7 @@ static int ti_eqep_function_write(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function function)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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enum ti_eqep_count_func qsrc;
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switch (function) {
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@ -179,7 +212,7 @@ static int ti_eqep_action_read(struct counter_device *counter,
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struct counter_synapse *synapse,
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enum counter_synapse_action *action)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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enum counter_function function;
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u32 qdecctl;
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int err;
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@ -239,19 +272,56 @@ static int ti_eqep_action_read(struct counter_device *counter,
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}
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}
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static int ti_eqep_events_configure(struct counter_device *counter)
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{
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struct ti_eqep_cnt *priv = counter_priv(counter);
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struct counter_event_node *event_node;
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u32 qeint = 0;
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list_for_each_entry(event_node, &counter->events_list, l) {
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switch (event_node->event) {
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case COUNTER_EVENT_OVERFLOW:
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qeint |= QEINT_PCO;
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break;
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case COUNTER_EVENT_UNDERFLOW:
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qeint |= QEINT_PCU;
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break;
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}
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}
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return regmap_write(priv->regmap16, QEINT, qeint);
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}
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static int ti_eqep_watch_validate(struct counter_device *counter,
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const struct counter_watch *watch)
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{
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switch (watch->event) {
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case COUNTER_EVENT_OVERFLOW:
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case COUNTER_EVENT_UNDERFLOW:
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if (watch->channel != 0)
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return -EINVAL;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct counter_ops ti_eqep_counter_ops = {
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.count_read = ti_eqep_count_read,
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.count_write = ti_eqep_count_write,
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.function_read = ti_eqep_function_read,
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.function_write = ti_eqep_function_write,
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.action_read = ti_eqep_action_read,
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.events_configure = ti_eqep_events_configure,
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.watch_validate = ti_eqep_watch_validate,
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};
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static int ti_eqep_position_ceiling_read(struct counter_device *counter,
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struct counter_count *count,
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u64 *ceiling)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 qposmax;
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regmap_read(priv->regmap32, QPOSMAX, &qposmax);
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@ -265,7 +335,7 @@ static int ti_eqep_position_ceiling_write(struct counter_device *counter,
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struct counter_count *count,
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u64 ceiling)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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if (ceiling != (u32)ceiling)
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return -ERANGE;
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@ -278,7 +348,7 @@ static int ti_eqep_position_ceiling_write(struct counter_device *counter,
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static int ti_eqep_position_enable_read(struct counter_device *counter,
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struct counter_count *count, u8 *enable)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 qepctl;
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regmap_read(priv->regmap16, QEPCTL, &qepctl);
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@ -291,7 +361,7 @@ static int ti_eqep_position_enable_read(struct counter_device *counter,
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static int ti_eqep_position_enable_write(struct counter_device *counter,
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struct counter_count *count, u8 enable)
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{
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struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
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struct ti_eqep_cnt *priv = counter_priv(counter);
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regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, enable ? -1 : 0);
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@ -355,6 +425,25 @@ static struct counter_count ti_eqep_counts[] = {
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},
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};
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static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id)
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{
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struct counter_device *counter = dev_id;
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 qflg;
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regmap_read(priv->regmap16, QFLG, &qflg);
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if (qflg & QFLG_PCO)
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counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0);
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if (qflg & QFLG_PCU)
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counter_push_event(counter, COUNTER_EVENT_UNDERFLOW, 0);
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regmap_write(priv->regmap16, QCLR, qflg);
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return IRQ_HANDLED;
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}
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static const struct regmap_config ti_eqep_regmap32_config = {
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.name = "32-bit",
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.reg_bits = 32,
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@ -378,7 +467,7 @@ static int ti_eqep_probe(struct platform_device *pdev)
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struct ti_eqep_cnt *priv;
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void __iomem *base;
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struct clk *clk;
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int err;
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int err, irq;
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counter = devm_counter_alloc(dev, sizeof(*priv));
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if (!counter)
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@ -399,6 +488,15 @@ static int ti_eqep_probe(struct platform_device *pdev)
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if (IS_ERR(priv->regmap16))
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return PTR_ERR(priv->regmap16);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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err = devm_request_threaded_irq(dev, irq, NULL, ti_eqep_irq_handler,
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IRQF_ONESHOT, dev_name(dev), counter);
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if (err < 0)
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return dev_err_probe(dev, err, "failed to request IRQ\n");
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counter->name = dev_name(dev);
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counter->parent = dev;
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counter->ops = &ti_eqep_counter_ops;
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@ -443,6 +541,7 @@ static void ti_eqep_remove(struct platform_device *pdev)
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static const struct of_device_id ti_eqep_of_match[] = {
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{ .compatible = "ti,am3352-eqep", },
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{ .compatible = "ti,am62-eqep", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ti_eqep_of_match);
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