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Qualcomm clock fixes for v6.12
Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks. Fix alpha PLL post_div mask for the cases where width is not specified. Enable the use of the recently introduced HW_CTRL trigger feature for SM8350 video clocks, to avoid hangs in the venus driver. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmcmqgcVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FIokQAKvZhVoBoDBaxZGjnGDPO0DNXDjy 9rMLg7S0n/UGrPTMrcM3JidiR7wucAuAIuqVaDkwAO9kDCxjczcucZw5sU46exlM 9u5nPicnTYHpoA5qjljovLmxba8ozKQta0ebynHZkBJRA1kcdkPGiYUTpBj69YXt QZjzMhbcKktqeJTqMUCX+PiTNpfkdjUhSBNvxW0628IQyMA133e6lBhp2GQyU8Sp FfqisDeuvEt9nSVyC13J/n755RcP9XKGX3YMP9ohZtjKxQNFKhn40AdR3x3e6zx+ fJ0FxNedNWXEhS9kxgjGEsqh0tP7X96x7g0EE4OrYrNErbrKBk679Dohxbsv5Bhx s9NwBjm8Nwe0U6qZ3cH/uaEzLo6KufrVV9y7lRO46y0yRbEphd1LY0ZAlQ8AX1hU 3RJjIaetQsZM0M93jJV/AE5w7yXkOJzz5wgwdYsGAClD4TJitPdNvFgtid9MlBoP 2rJOthmn3btCu6PbFGq+aFDNuLjJ/h9GaBAlcmkqCb+wtUC+G39sZqb/IQNOHeyK 4uAEb0tyN+ghN0nR0MuP2DBQ7f1r0kckPF+n4pWcJ0H19FM3MbhJ3OL+Sx/SPjPh zzxYmBJVRBy6fplBuwBSOUuMwpY1M7kjjmnrViShK9dqwod7V1ijpWRd/9W7+ycK BFeccHrzvHECci9x =y0zK -----END PGP SIGNATURE----- Merge tag 'qcom-clk-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull Qualcomm clk driver fixes from Bjorn Andersson: - Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks - Fix alpha PLL post_div mask for the cases where width is not specified - Avoid hangs in the SM8350 video driver (venus) by setting HW_CTRL trigger feature on the video clocks * tag 'qcom-clk-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set clk: qcom: videocc-sm8350: use HW_CTRL_TRIGGER for vcodec GDSCs
This commit is contained in:
commit
714398d874
@ -40,7 +40,7 @@
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#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
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# define PLL_POST_DIV_SHIFT 8
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# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
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# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
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# define PLL_ALPHA_MSB BIT(15)
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# define PLL_ALPHA_EN BIT(24)
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# define PLL_ALPHA_MODE BIT(25)
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@ -3123,7 +3123,7 @@ static struct clk_branch gcc_pcie_3_pipe_clk = {
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static struct clk_branch gcc_pcie_3_pipediv2_clk = {
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.halt_reg = 0x58060,
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.halt_check = BRANCH_HALT_VOTED,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x52020,
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.enable_mask = BIT(5),
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@ -3248,7 +3248,7 @@ static struct clk_branch gcc_pcie_4_pipe_clk = {
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static struct clk_branch gcc_pcie_4_pipediv2_clk = {
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.halt_reg = 0x6b054,
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.halt_check = BRANCH_HALT_VOTED,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x52010,
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.enable_mask = BIT(27),
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@ -3373,7 +3373,7 @@ static struct clk_branch gcc_pcie_5_pipe_clk = {
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static struct clk_branch gcc_pcie_5_pipediv2_clk = {
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.halt_reg = 0x2f054,
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.halt_check = BRANCH_HALT_VOTED,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x52018,
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.enable_mask = BIT(19),
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@ -3511,7 +3511,7 @@ static struct clk_branch gcc_pcie_6a_pipe_clk = {
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static struct clk_branch gcc_pcie_6a_pipediv2_clk = {
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.halt_reg = 0x31060,
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.halt_check = BRANCH_HALT_VOTED,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x52018,
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.enable_mask = BIT(28),
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@ -3649,7 +3649,7 @@ static struct clk_branch gcc_pcie_6b_pipe_clk = {
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static struct clk_branch gcc_pcie_6b_pipediv2_clk = {
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.halt_reg = 0x8d060,
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.halt_check = BRANCH_HALT_VOTED,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x52010,
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.enable_mask = BIT(28),
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@ -6155,7 +6155,7 @@ static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
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.pd = {
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.name = "gcc_usb3_mp_ss1_phy_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.pwrsts = PWRSTS_RET_ON,
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.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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};
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@ -452,7 +452,7 @@ static struct gdsc mvs0_gdsc = {
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.pd = {
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.name = "mvs0_gdsc",
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},
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.flags = HW_CTRL | RETAIN_FF_ENABLE,
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.flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE,
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.pwrsts = PWRSTS_OFF_ON,
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};
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@ -461,7 +461,7 @@ static struct gdsc mvs1_gdsc = {
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.pd = {
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.name = "mvs1_gdsc",
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},
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.flags = HW_CTRL | RETAIN_FF_ENABLE,
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.flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE,
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.pwrsts = PWRSTS_OFF_ON,
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};
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