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spi: imx: support word delay in ecspi
Merge series from Jonas Rebmann <jre@pengutronix.de>: The i.MX SPI controller supports inserting a configurable delay between subsequent words, which is needed for some slower devices that couldn't keep up otherwise. This patch series introduces support for the word delay parameters for i.MX51 onwards. The SPI clock (CSRC=0) was chosen as the clock source over the also available 32.768 KHz Low-Frequency Reference Clock (CSRC=1). The sample period control bits (SAMPLE_PERIOD) are set to the selected word delay converted to SPI clock cycles. A deviation from the requested number of wait cycles and the actual word delay was observed via both software timings and oscilloscope measurements and accounted for. The Chip Select Delay Control bits in the Sample Period Control Register remain zero. Behaviour on i.MX35 and earlier, where the CSPI interface is used, remains unchanged.
This commit is contained in:
Mark Brown
commit
26470a2e87
@ -3,6 +3,7 @@
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// Copyright (C) 2008 Juergen Beisert
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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@ -13,7 +14,10 @@
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/math.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/overflow.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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@ -71,7 +75,8 @@ struct spi_imx_data;
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struct spi_imx_devtype_data {
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void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
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int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
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int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
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int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi,
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struct spi_transfer *t);
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void (*trigger)(struct spi_imx_data *spi_imx);
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int (*rx_available)(struct spi_imx_data *spi_imx);
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void (*reset)(struct spi_imx_data *spi_imx);
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@ -301,6 +306,18 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
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#define MX51_ECSPI_STAT 0x18
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#define MX51_ECSPI_STAT_RR (1 << 3)
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#define MX51_ECSPI_PERIOD 0x1c
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#define MX51_ECSPI_PERIOD_MASK 0x7fff
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/*
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* As measured on the i.MX6, the SPI host controller inserts a 4 SPI-Clock
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* (SCLK) delay after each burst if the PERIOD reg is 0x0. This value will be
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* called MX51_ECSPI_PERIOD_MIN_DELAY_SCK.
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*
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* If the PERIOD register is != 0, the controller inserts a delay of
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* MX51_ECSPI_PERIOD_MIN_DELAY_SCK + register value + 1 SCLK after each burst.
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*/
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#define MX51_ECSPI_PERIOD_MIN_DELAY_SCK 4
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#define MX51_ECSPI_TESTREG 0x20
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#define MX51_ECSPI_TESTREG_LBC BIT(31)
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@ -648,9 +665,10 @@ static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
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}
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static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
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struct spi_device *spi)
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struct spi_device *spi, struct spi_transfer *t)
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{
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u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
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u64 word_delay_sck;
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u32 clk;
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/* Clear BL field and set the right value */
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@ -682,6 +700,49 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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/* calculate word delay in SPI Clock (SCLK) cycles */
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if (t->word_delay.value == 0) {
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word_delay_sck = 0;
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} else if (t->word_delay.unit == SPI_DELAY_UNIT_SCK) {
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word_delay_sck = t->word_delay.value;
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if (word_delay_sck <= MX51_ECSPI_PERIOD_MIN_DELAY_SCK)
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word_delay_sck = 0;
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else if (word_delay_sck <= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1)
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word_delay_sck = 1;
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else
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word_delay_sck -= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1;
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} else {
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int word_delay_ns;
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word_delay_ns = spi_delay_to_ns(&t->word_delay, t);
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if (word_delay_ns < 0)
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return word_delay_ns;
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if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC,
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MX51_ECSPI_PERIOD_MIN_DELAY_SCK,
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spi_imx->spi_bus_clk)) {
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word_delay_sck = 0;
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} else if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC,
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MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1,
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spi_imx->spi_bus_clk)) {
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word_delay_sck = 1;
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} else {
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word_delay_ns -= mul_u64_u32_div(NSEC_PER_SEC,
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MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1,
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spi_imx->spi_bus_clk);
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word_delay_sck = DIV_U64_ROUND_UP((u64)word_delay_ns * spi_imx->spi_bus_clk,
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NSEC_PER_SEC);
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}
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}
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if (!FIELD_FIT(MX51_ECSPI_PERIOD_MASK, word_delay_sck))
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return -EINVAL;
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writel(FIELD_PREP(MX51_ECSPI_PERIOD_MASK, word_delay_sck),
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spi_imx->base + MX51_ECSPI_PERIOD);
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return 0;
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}
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@ -773,7 +834,7 @@ static int mx31_prepare_message(struct spi_imx_data *spi_imx,
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}
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static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
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struct spi_device *spi)
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struct spi_device *spi, struct spi_transfer *t)
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{
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST;
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unsigned int clk;
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@ -877,7 +938,7 @@ static int mx21_prepare_message(struct spi_imx_data *spi_imx,
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}
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static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
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struct spi_device *spi)
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struct spi_device *spi, struct spi_transfer *t)
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{
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unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST;
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unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
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@ -952,7 +1013,7 @@ static int mx1_prepare_message(struct spi_imx_data *spi_imx,
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}
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static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
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struct spi_device *spi)
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struct spi_device *spi, struct spi_transfer *t)
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{
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unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST;
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unsigned int clk;
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@ -1262,11 +1323,13 @@ static int spi_imx_setupxfer(struct spi_device *spi,
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/*
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* Initialize the functions for transfer. To transfer non byte-aligned
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* words, we have to use multiple word-size bursts, we can't use
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* dynamic_burst in that case.
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* words, we have to use multiple word-size bursts. To insert word
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* delay, the burst size has to equal the word size. We can't use
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* dynamic_burst in these cases.
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*/
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if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode &&
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!(spi->mode & SPI_CS_WORD) &&
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!(t->word_delay.value) &&
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(spi_imx->bits_per_word == 8 ||
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spi_imx->bits_per_word == 16 ||
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spi_imx->bits_per_word == 32)) {
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@ -1303,7 +1366,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
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spi_imx->target_burst = t->len;
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}
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spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
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spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
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return 0;
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}
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@ -1609,12 +1672,30 @@ static int spi_imx_pio_transfer_target(struct spi_device *spi,
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return ret;
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}
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static unsigned int spi_imx_transfer_estimate_time_us(struct spi_transfer *transfer)
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{
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u64 result;
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result = DIV_U64_ROUND_CLOSEST((u64)USEC_PER_SEC * transfer->len * BITS_PER_BYTE,
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transfer->effective_speed_hz);
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if (transfer->word_delay.value) {
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unsigned int word_delay_us;
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unsigned int words;
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words = DIV_ROUND_UP(transfer->len * BITS_PER_BYTE, transfer->bits_per_word);
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word_delay_us = DIV_ROUND_CLOSEST(spi_delay_to_ns(&transfer->word_delay, transfer),
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NSEC_PER_USEC);
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result += words * word_delay_us;
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}
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return min(result, U32_MAX);
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}
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static int spi_imx_transfer_one(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
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unsigned long hz_per_byte, byte_limit;
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spi_imx_setupxfer(spi, transfer);
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transfer->effective_speed_hz = spi_imx->spi_bus_clk;
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@ -1633,15 +1714,10 @@ static int spi_imx_transfer_one(struct spi_controller *controller,
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*/
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if (spi_imx->usedma)
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return spi_imx_dma_transfer(spi_imx, transfer);
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/*
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* Calculate the estimated time in us the transfer runs. Find
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* the number of Hz per byte per polling limit.
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*/
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hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0;
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byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1;
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/* run in polling mode for short transfers */
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if (transfer->len < byte_limit)
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if (transfer->len == 1 || (polling_limit_us &&
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spi_imx_transfer_estimate_time_us(transfer) < polling_limit_us))
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return spi_imx_poll_transfer(spi, transfer);
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return spi_imx_pio_transfer(spi, transfer);
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