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A few more Qualcomm driver updates for v6.13

Browse Source 
Make the Adreno driver invoke the SMMU aperture setup firmware function,
 which is required to allow the GPU to manage per-process page tables in
 some firmware versions - as an example Rb3Gen2 has no GPU without this.
 
 Add X1E Devkit to the list of devices that has functional EFI variable
 access through the uefisecapp.
 
 Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
 as this only applies to a single platform, and introduce support for
 QCS8300, QCS615, SAR2130P, and SAR1130P.
 
 Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.
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Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

A few more Qualcomm driver updates for v6.13

Make the Adreno driver invoke the SMMU aperture setup firmware function,
which is required to allow the GPU to manage per-process page tables in
some firmware versions - as an example Rb3Gen2 has no GPU without this.

Add X1E Devkit to the list of devices that has functional EFI variable
access through the uefisecapp.

Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
as this only applies to a single platform, and introduce support for
QCS8300, QCS615, SAR2130P, and SAR1130P.

Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.

* tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: ice: Remove the device_link field in qcom_ice
  drm/msm/adreno: Setup SMMU aparture for per-process page table
  firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
  soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
  soc: qcom: llcc: Flip the manual slice configuration condition
  dt-bindings: firmware: qcom,scm: Document sm8750 SCM
  firmware: qcom: uefisecapp: Allow X1E Devkit devices
  soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
  dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
  soc: qcom: llcc: Add configuration data for QCS615
  dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
  soc: qcom: llcc: add support for SAR2130P and SAR1130P
  soc: qcom: llcc: use deciman integers for bit shift values
  dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-11-13 18:38:51 +01:00
commit 1876c788bb
11 changed files with 676 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View File

@ -20,8 +20,12 @@ description: |
properties:
compatible:
enum:
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
- qcom,sa8775p-llcc
- qcom,sar1130p-llcc
- qcom,sar2130p-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
@ -67,6 +71,33 @@ allOf:
compatible:
contains:
enum:
- qcom,sar1130p-llcc
- qcom,sar2130p-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC broadcast OR register region
- description: LLCC broadcast AND register region
- description: LLCC scratchpad broadcast OR register region
- description: LLCC scratchpad broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
- const: llcc_scratchpad_broadcast_base
- const: llcc_scratchpad_broadcast_and_base
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs615-llcc
- qcom,sc7180-llcc
- qcom,sm6350-llcc
then:
@ -165,6 +196,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qcs8300-llcc
- qcom,sdm845-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc

2
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View File

@ -67,6 +67,7 @@ properties:
- qcom,scm-sm8450
- qcom,scm-sm8550
- qcom,scm-sm8650
- qcom,scm-sm8750
- qcom,scm-qcs404
- qcom,scm-x1e80100
- const: qcom,scm
@ -198,6 +199,7 @@ allOf:
- qcom,scm-sm8450
- qcom,scm-sm8550
- qcom,scm-sm8650
- qcom,scm-sm8750
then:
properties:
interrupts: false

27
drivers/firmware/qcom/qcom_scm.c
View File

@ -903,6 +903,32 @@ int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
}
EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg);
#define QCOM_SCM_CP_APERTURE_CONTEXT_MASK GENMASK(7, 0)
bool qcom_scm_set_gpu_smmu_aperture_is_available(void)
{
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
QCOM_SCM_MP_CP_SMMU_APERTURE_ID);
}
EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture_is_available);
int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_MP,
.cmd = QCOM_SCM_MP_CP_SMMU_APERTURE_ID,
.arginfo = QCOM_SCM_ARGS(4),
.args[0] = 0xffff0000 | FIELD_PREP(QCOM_SCM_CP_APERTURE_CONTEXT_MASK, context_bank),
.args[1] = 0xffffffff,
.args[2] = 0xffffffff,
.args[3] = 0xffffffff,
.owner = ARM_SMCCC_OWNER_SIP
};
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture);
int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
{
struct qcom_scm_desc desc = {
@ -1740,6 +1766,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
{ .compatible = "microsoft,romulus13", },
{ .compatible = "microsoft,romulus15", },
{ .compatible = "qcom,sc8180x-primus" },
{ .compatible = "qcom,x1e001de-devkit" },
{ .compatible = "qcom,x1e80100-crd" },
{ .compatible = "qcom,x1e80100-qcp" },
{ }

1
drivers/firmware/qcom/qcom_scm.h
View File

@ -116,6 +116,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void);
#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05
#define QCOM_SCM_MP_VIDEO_VAR 0x08
#define QCOM_SCM_MP_ASSIGN 0x16
#define QCOM_SCM_MP_CP_SMMU_APERTURE_ID 0x1b
#define QCOM_SCM_MP_SHM_BRIDGE_ENABLE 0x1c
#define QCOM_SCM_MP_SHM_BRIDGE_DELETE 0x1d
#define QCOM_SCM_MP_SHM_BRIDGE_CREATE 0x1e

11
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -572,8 +572,19 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
int adreno_hw_init(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int ret;
VERB("%s", gpu->name);
if (adreno_gpu->info->family >= ADRENO_6XX_GEN1 &&
qcom_scm_set_gpu_smmu_aperture_is_available()) {
/* We currently always use context bank 0, so hard code this */
ret = qcom_scm_set_gpu_smmu_aperture(0);
if (ret)
DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret);
}
for (int i = 0; i < gpu->nr_rings; i++) {
struct msm_ringbuffer *ring = gpu->rb[i];

6
drivers/soc/qcom/ice.c
View File

@ -44,7 +44,6 @@
struct qcom_ice {
struct device *dev;
void __iomem *base;
struct device_link *link;
struct clk *core_clk;
};
@ -268,6 +267,7 @@ struct qcom_ice *of_qcom_ice_get(struct device *dev)
struct qcom_ice *ice;
struct resource *res;
void __iomem *base;
struct device_link *link;
if (!dev || !dev->of_node)
return ERR_PTR(-ENODEV);
@ -311,8 +311,8 @@ struct qcom_ice *of_qcom_ice_get(struct device *dev)
return ERR_PTR(-EPROBE_DEFER);
}
ice->link = device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER);
if (!ice->link) {
link = device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER);
if (!link) {
dev_err(&pdev->dev,
"Failed to create device link to consumer %s\n",
dev_name(dev));

615
drivers/soc/qcom/llcc-qcom.c
View File

@ -27,14 +27,14 @@
#define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
#define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
#define ACT_CTRL_ACT_TRIG BIT(0)
#define ACT_CTRL_OPCODE_SHIFT 0x01
#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
#define ATTR1_FIXED_SIZE_SHIFT 0x03
#define ATTR1_PRIORITY_SHIFT 0x04
#define ATTR1_MAX_CAP_SHIFT 0x10
#define ACT_CTRL_OPCODE_SHIFT 1
#define ATTR1_PROBE_TARGET_WAYS_SHIFT 2
#define ATTR1_FIXED_SIZE_SHIFT 3
#define ATTR1_PRIORITY_SHIFT 4
#define ATTR1_MAX_CAP_SHIFT 16
#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
#define ATTR0_BONUS_WAYS_SHIFT 0x10
#define ATTR0_BONUS_WAYS_SHIFT 16
#define LLCC_STATUS_READ_DELAY 100
#define CACHE_LINE_SIZE_SHIFT 6
@ -136,8 +136,10 @@ struct qcom_llcc_config {
const struct llcc_slice_config *sct_data;
const u32 *reg_offset;
const struct llcc_edac_reg_offset *edac_reg_offset;
u32 max_cap_shift; /* instead of ATTR1_MAX_CAP_SHIFT */
u32 num_banks;
int size;
bool need_llcc_cfg;
bool skip_llcc_cfg;
bool no_edac;
};
@ -297,6 +299,408 @@ static const struct llcc_slice_config sa8775p_data[] = {
},
};
static const struct llcc_slice_config sar1130p_data[] = {
{
.usecase_id = LLCC_CPUSS,
.slice_id = 1,
.max_cap = 4096,
.priority = 1,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
.activate_on_init = true,
}, {
.usecase_id = LLCC_VIDSC0,
.slice_id = 2,
.max_cap = 512,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_AUDIO,
.slice_id = 6,
.max_cap = 1024,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_CMPT,
.slice_id = 10,
.max_cap = 1024,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 12,
.max_cap = 3072,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
.write_scid_en = true,
}, {
.usecase_id = LLCC_MMUHWT,
.slice_id = 13,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
}, {
.usecase_id = LLCC_DISP,
.slice_id = 16,
.max_cap = 12800,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_CVP,
.slice_id = 28,
.max_cap = 256,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_APTCM,
.slice_id = 26,
.max_cap = 2048,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x3,
.cache_mode = true,
.dis_cap_alloc = true,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_WRCACHE,
.slice_id = 31,
.max_cap = 256,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_AENPU,
.slice_id = 30,
.max_cap = 3072,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x1fff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_DISP_LEFT,
.slice_id = 17,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_DISP_RIGHT,
.slice_id = 18,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVCS_LEFT,
.slice_id = 22,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVCS_RIGHT,
.slice_id = 23,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
},
};
static const struct llcc_slice_config sar2130p_data[] = {
{
.usecase_id = LLCC_CPUSS,
.slice_id = 1,
.max_cap = 6144,
.priority = 1,
.fixed_size = 0,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
.activate_on_init = true,
}, {
.usecase_id = LLCC_VIDSC0,
.slice_id = 2,
.max_cap = 128,
.priority = 2,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_AUDIO,
.slice_id = 6,
.max_cap = 1024,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_CMPT,
.slice_id = 10,
.max_cap = 1024,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 12,
.max_cap = 1536,
.priority = 2,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
.write_scid_en = true,
}, {
.usecase_id = LLCC_MMUHWT,
.slice_id = 13,
.max_cap = 1024,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_DISP,
.slice_id = 16,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_APTCM,
.slice_id = 26,
.max_cap = 2048,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x3,
.cache_mode = true,
.dis_cap_alloc = true,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_WRCACHE,
.slice_id = 31,
.max_cap = 256,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_VIEYE,
.slice_id = 7,
.max_cap = 7168,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_VIDPTH,
.slice_id = 8,
.max_cap = 7168,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_GPUMV,
.slice_id = 9,
.max_cap = 2048,
.priority = 2,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVA_LEFT,
.slice_id = 20,
.max_cap = 7168,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0x3ffffffc,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVA_RIGHT,
.slice_id = 21,
.max_cap = 7168,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0x3ffffffc,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVAGAIN,
.slice_id = 25,
.max_cap = 1024,
.priority = 2,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_AENPU,
.slice_id = 30,
.max_cap = 3072,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_VIPTH,
.slice_id = 29,
.max_cap = 1024,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0x3fffffff,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_DISP_LEFT,
.slice_id = 17,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_DISP_RIGHT,
.slice_id = 18,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVCS_LEFT,
.slice_id = 22,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_EVCS_RIGHT,
.slice_id = 23,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_SPAD,
.slice_id = 24,
.max_cap = 7168,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0x0,
.res_ways = 0x0,
.cache_mode = 0,
.retain_on_pc = true,
},
};
static const struct llcc_slice_config sc7180_data[] = {
{
.usecase_id = LLCC_CPUSS,
@ -2224,6 +2628,95 @@ static const struct llcc_slice_config sm8650_data[] = {
},
};
static const struct llcc_slice_config qcs615_data[] = {
{
.usecase_id = LLCC_CPUSS,
.slice_id = 1,
.max_cap = 128,
.priority = 1,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
.write_scid_en = true,
}, {
.usecase_id = LLCC_MDM,
.slice_id = 8,
.max_cap = 256,
.priority = 0,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 128,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 12,
.max_cap = 128,
.priority = 1,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
},
};
static const struct llcc_slice_config qcs8300_data[] = {
{
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 128,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.retain_on_pc = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 12,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.retain_on_pc = true,
.write_scid_en = true,
}, {
.usecase_id = LLCC_MMUHWT,
.slice_id = 13,
.max_cap = 128,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_ECC,
.slice_id = 26,
.max_cap = 256,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
}, {
.usecase_id = LLCC_WRCACHE,
.slice_id = 31,
.max_cap = 128,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xf,
.cache_mode = 0,
.activate_on_init = true,
},
};
static const struct llcc_slice_config qdu1000_data_2ch[] = {
{
.usecase_id = LLCC_MDMHPGRW,
@ -2645,32 +3138,47 @@ static const u32 llcc_v2_1_reg_offset[] = {
[LLCC_COMMON_STATUS0] = 0x0003400c,
};
static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
.size = ARRAY_SIZE(qcs615_data),
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
};
static const struct qcom_llcc_config qcs8300_cfg[] = {
{
.sct_data = qcs8300_data,
.size = ARRAY_SIZE(qcs8300_data),
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
.num_banks = 4,
},
};
static const struct qcom_llcc_config qdu1000_cfg[] = {
{
.sct_data = qdu1000_data_8ch,
.size = ARRAY_SIZE(qdu1000_data_8ch),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
{
.sct_data = qdu1000_data_4ch,
.size = ARRAY_SIZE(qdu1000_data_4ch),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
{
.sct_data = qdu1000_data_4ch,
.size = ARRAY_SIZE(qdu1000_data_4ch),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
{
.sct_data = qdu1000_data_2ch,
.size = ARRAY_SIZE(qdu1000_data_2ch),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
@ -2680,17 +3188,37 @@ static const struct qcom_llcc_config sa8775p_cfg[] = {
{
.sct_data = sa8775p_data,
.size = ARRAY_SIZE(sa8775p_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
};
static const struct qcom_llcc_config sar1130p_cfg[] = {
{
.sct_data = sar1130p_data,
.size = ARRAY_SIZE(sar1130p_data),
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
.max_cap_shift = 14,
.num_banks = 2,
},
};
static const struct qcom_llcc_config sar2130p_cfg[] = {
{
.sct_data = sar2130p_data,
.size = ARRAY_SIZE(sar2130p_data),
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
.max_cap_shift = 14,
.num_banks = 2,
},
};
static const struct qcom_llcc_config sc7180_cfg[] = {
{
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2700,7 +3228,6 @@ static const struct qcom_llcc_config sc7280_cfg[] = {
{
.sct_data = sc7280_data,
.size = ARRAY_SIZE(sc7280_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2710,7 +3237,6 @@ static const struct qcom_llcc_config sc8180x_cfg[] = {
{
.sct_data = sc8180x_data,
.size = ARRAY_SIZE(sc8180x_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2720,7 +3246,6 @@ static const struct qcom_llcc_config sc8280xp_cfg[] = {
{
.sct_data = sc8280xp_data,
.size = ARRAY_SIZE(sc8280xp_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2730,7 +3255,7 @@ static const struct qcom_llcc_config sdm845_cfg[] = {
{
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
.need_llcc_cfg = false,
.skip_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
.no_edac = true,
@ -2741,7 +3266,6 @@ static const struct qcom_llcc_config sm6350_cfg[] = {
{
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2751,7 +3275,6 @@ static const struct qcom_llcc_config sm7150_cfg[] = {
{
.sct_data = sm7150_data,
.size = ARRAY_SIZE(sm7150_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2761,7 +3284,6 @@ static const struct qcom_llcc_config sm8150_cfg[] = {
{
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2771,7 +3293,6 @@ static const struct qcom_llcc_config sm8250_cfg[] = {
{
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2781,7 +3302,6 @@ static const struct qcom_llcc_config sm8350_cfg[] = {
{
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v1_reg_offset,
.edac_reg_offset = &llcc_v1_edac_reg_offset,
},
@ -2791,7 +3311,6 @@ static const struct qcom_llcc_config sm8450_cfg[] = {
{
.sct_data = sm8450_data,
.size = ARRAY_SIZE(sm8450_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
@ -2801,7 +3320,6 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
{
.sct_data = sm8550_data,
.size = ARRAY_SIZE(sm8550_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
@ -2811,7 +3329,6 @@ static const struct qcom_llcc_config sm8650_cfg[] = {
{
.sct_data = sm8650_data,
.size = ARRAY_SIZE(sm8650_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
@ -2821,12 +3338,21 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
{
.sct_data = x1e80100_data,
.size = ARRAY_SIZE(x1e80100_data),
.need_llcc_cfg = true,
.reg_offset = llcc_v2_1_reg_offset,
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
},
};
static const struct qcom_sct_config qcs615_cfgs = {
.llcc_config = qcs615_cfg,
.num_config = ARRAY_SIZE(qcs615_cfg),
};
static const struct qcom_sct_config qcs8300_cfgs = {
.llcc_config = qcs8300_cfg,
.num_config = ARRAY_SIZE(qcs8300_cfg),
};
static const struct qcom_sct_config qdu1000_cfgs = {
.llcc_config = qdu1000_cfg,
.num_config = ARRAY_SIZE(qdu1000_cfg),
@ -2837,6 +3363,16 @@ static const struct qcom_sct_config sa8775p_cfgs = {
.num_config = ARRAY_SIZE(sa8775p_cfg),
};
static const struct qcom_sct_config sar1130p_cfgs = {
.llcc_config = sar1130p_cfg,
.num_config = ARRAY_SIZE(sar1130p_cfg),
};
static const struct qcom_sct_config sar2130p_cfgs = {
.llcc_config = sar2130p_cfg,
.num_config = ARRAY_SIZE(sar2130p_cfg),
};
static const struct qcom_sct_config sc7180_cfgs = {
.llcc_config = sc7180_cfg,
.num_config = ARRAY_SIZE(sc7180_cfg),
@ -3144,7 +3680,10 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
*/
max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
if (cfg->max_cap_shift)
attr1_val |= max_cap_cacheline << cfg->max_cap_shift;
else
attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
@ -3173,7 +3712,8 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
return ret;
}
if (cfg->need_llcc_cfg) {
/* At least SDM845 disallows non-secure writes to these registers */
if (!cfg->skip_llcc_cfg) {
u32 disable_cap_alloc, retain_pc;
disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
@ -3381,12 +3921,17 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
cfg = &cfgs->llcc_config[cfg_index];
ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
if (ret)
goto err;
if (cfg->num_banks) {
num_banks = cfg->num_banks;
} else {
ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
if (ret)
goto err;
num_banks &= LLCC_LB_CNT_MASK;
num_banks >>= LLCC_LB_CNT_SHIFT;
}
num_banks &= LLCC_LB_CNT_MASK;
num_banks >>= LLCC_LB_CNT_SHIFT;
drv_data->num_banks = num_banks;
drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL);
@ -3481,8 +4026,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
{ .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs},
{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
{ .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs },
{ .compatible = "qcom,sar1130p-llcc", .data = &sar1130p_cfgs },
{ .compatible = "qcom,sar2130p-llcc", .data = &sar2130p_cfgs },
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },

2
drivers/soc/qcom/socinfo.c
View File

@ -446,6 +446,8 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(QCM8550) },
{ qcom_board_id(IPQ5300) },
{ qcom_board_id(IPQ5321) },
{ qcom_board_id(IPQ5424) },
{ qcom_board_id(IPQ5404) },
{ qcom_board_id(QCS9100) },
{ qcom_board_id(QCS8300) },
{ qcom_board_id(QCS8275) },

2
include/dt-bindings/arm/qcom,ids.h
View File

@ -279,6 +279,8 @@
#define QCOM_ID_QCM8550 604
#define QCOM_ID_IPQ5300 624
#define QCOM_ID_IPQ5321 650
#define QCOM_ID_IPQ5424 651
#define QCOM_ID_IPQ5404 671
#define QCOM_ID_QCS9100 667
#define QCOM_ID_QCS8300 674
#define QCOM_ID_QCS8275 675

2
include/linux/firmware/qcom/qcom_scm.h
View File

@ -85,6 +85,8 @@ int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
bool qcom_scm_restore_sec_cfg_available(void);
int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank);
bool qcom_scm_set_gpu_smmu_aperture_is_available(void);
int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);

12
include/linux/soc/qcom/llcc-qcom.h
View File

@ -54,7 +54,19 @@
#define LLCC_CAMEXP4 52
#define LLCC_DISP_WB 53
#define LLCC_DISP_1 54
#define LLCC_VIEYE 57
#define LLCC_VIDPTH 58
#define LLCC_GPUMV 59
#define LLCC_EVA_LEFT 60
#define LLCC_EVA_RIGHT 61
#define LLCC_EVAGAIN 62
#define LLCC_VIPTH 63
#define LLCC_VIDVSP 64
#define LLCC_DISP_LEFT 65
#define LLCC_DISP_RIGHT 66
#define LLCC_EVCS_LEFT 67
#define LLCC_EVCS_RIGHT 68
#define LLCC_SPAD 69
/**
* struct llcc_slice_desc - Cache slice descriptor