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RISC-V: Fix asm checks regression due to recent middle-end change

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The recent middle-end change result in some asm check failures.
This patch would like to fix the asm check by adjust the times.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/shift-1.c: Fix asm check
	count.
	* gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2024-01-17 16:56:56 +08:00
parent 3359942417
commit de4c9a27ba
3 changed files with 3 additions and 3 deletions
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2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
View File

@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>)
DEF_OP_VV (shift, 256, int64_t, >>)
DEF_OP_VV (shift, 512, int64_t, >>)
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
/* { dg-final { scan-assembler-not {csrr} } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
View File

@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>)
DEF_OP_VV (shift, 256, uint64_t, >>)
DEF_OP_VV (shift, 512, uint64_t, >>)
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
/* { dg-final { scan-assembler-not {csrr} } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
View File

@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, <<)
DEF_OP_VV (shift, 256, int64_t, <<)
DEF_OP_VV (shift, 512, int64_t, <<)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 46 } } */
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */
/* { dg-final { scan-assembler-not {csrr} } } */