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thumb2.md: Extend peephole to cover 3-arg subs.

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2008-03-12  Paul Brook  <paul@codesourcery.com>

	gcc/
	* config/arm/thumb2.md: Extend peephole to cover 3-arg subs.
	(thumb2_alusi3_short): Exclude PLUS and MINUS.
	(thumb2_addsi_shortim): Rename ...
	(thumb2_addsi_short): ... to this.  Allow register operands.
	(thumb2_subsi_short): New pattern.
	(thumb2_one_cmplsi2_short,
	thumb2_negsi2_short): New patterns and peepholes.

From-SVN: r133152
This commit is contained in:
Paul Brook 2008-03-12 23:19:41 +00:00 committed by Paul Brook
parent 0975490466
commit d1b85efbd4
2 changed files with 82 additions and 5 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2008-03-12 Paul Brook <paul@codesourcery.com>
* config/arm/thumb2.md: Extend peephole to cover 3-arg subs.
(thumb2_alusi3_short): Exclude PLUS and MINUS.
(thumb2_addsi_shortim): Rename ...
(thumb2_addsi_short): ... to this. Allow register operands.
(thumb2_subsi_short): New pattern.
(thumb2_one_cmplsi2_short,
thumb2_negsi2_short): New patterns and peepholes.
2008-03-12 Paul Brook <paul@codesourcery.com>
gcc/

77
gcc/config/arm/thumb2.md
View File

@ -1002,7 +1002,10 @@
(match_operator:SI 3 "thumb_16bit_operator"
[(match_operand:SI 1 "low_register_operand" "")
(match_operand:SI 2 "low_register_operand" "")]))]
"TARGET_THUMB2 && rtx_equal_p(operands[0], operands[1])
"TARGET_THUMB2
&& (rtx_equal_p(operands[0], operands[1])
|| GET_CODE(operands[3]) == PLUS
|| GET_CODE(operands[3]) == MINUS)
&& peep2_regno_dead_p(0, CC_REGNUM)"
[(parallel
[(set (match_dup 0)
@ -1019,7 +1022,9 @@
[(match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "l")]))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"TARGET_THUMB2 && reload_completed
&& GET_CODE(operands[3]) != PLUS
&& GET_CODE(operands[3]) != MINUS"
"%I3%!\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "length" "2")]
@ -1105,16 +1110,20 @@
""
)
(define_insn "*thumb2_addsi_shortim"
(define_insn "*thumb2_addsi_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
(plus:SI (match_operand:SI 1 "low_register_operand" "l")
(match_operand:SI 2 "const_int_operand" "IL")))
(match_operand:SI 2 "low_reg_or_int_operand" "lIL")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"*
HOST_WIDE_INT val;
val = INTVAL(operands[2]);
if (GET_CODE (operands[2]) == CONST_INT)
val = INTVAL(operands[2]);
else
val = 0;
/* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
return \"sub%!\\t%0, %1, #%n2\";
@ -1145,6 +1154,17 @@
(set_attr "insn" "udiv")]
)
(define_insn "*thumb2_subsi_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
(minus:SI (match_operand:SI 1 "low_register_operand" "l")
(match_operand:SI 2 "low_register_operand" "l")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"sub%!\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "length" "2")]
)
(define_insn "*thumb2_cbz"
[(set (pc) (if_then_else
(eq (match_operand:SI 0 "s_register_operand" "l,?r")
@ -1188,3 +1208,50 @@
(const_int 2)
(const_int 8)))]
)
;; 16-bit complement
(define_peephole2
[(set (match_operand:SI 0 "low_register_operand" "")
(not:SI (match_operand:SI 1 "low_register_operand" "")))]
"TARGET_THUMB2
&& peep2_regno_dead_p(0, CC_REGNUM)"
[(parallel
[(set (match_dup 0)
(not:SI (match_dup 1)))
(clobber (reg:CC CC_REGNUM))])]
""
)
(define_insn "*thumb2_one_cmplsi2_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
(not:SI (match_operand:SI 1 "low_register_operand" "l")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"mvn%!\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "length" "2")]
)
;; 16-bit negate
(define_peephole2
[(set (match_operand:SI 0 "low_register_operand" "")
(neg:SI (match_operand:SI 1 "low_register_operand" "")))]
"TARGET_THUMB2
&& peep2_regno_dead_p(0, CC_REGNUM)"
[(parallel
[(set (match_dup 0)
(neg:SI (match_dup 1)))
(clobber (reg:CC CC_REGNUM))])]
""
)
(define_insn "*thumb2_negsi2_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
(neg:SI (match_operand:SI 1 "low_register_operand" "l")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"neg%!\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "length" "2")]
)