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aarch64: Remove unnecessary casts to rtx_code [PR117349]
In aarch64_gen_ccmp_first/aarch64_gen_ccmp_next, the casts were no longer needed after r14-3412-gbf64392d66f291 which changed the type of the arguments to rtx_code. In aarch64_rtx_costs, they were no longer needed since r12-4828-g1d5c43db79b7ea which changed the type of code to rtx_code. Pushed as obvious after a build/test for aarch64-linux-gnu. gcc/ChangeLog: PR target/117349 * config/aarch64/aarch64.cc (aarch64_rtx_costs): Remove unnecessary casts to rtx_code. (aarch64_gen_ccmp_first): Likewise. (aarch64_gen_ccmp_next): Likewise. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
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@ -14286,7 +14286,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
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/* BFM. */
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if (speed)
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*cost += extra_cost->alu.bfi;
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*cost += rtx_cost (op1, VOIDmode, (enum rtx_code) code, 1, speed);
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*cost += rtx_cost (op1, VOIDmode, code, 1, speed);
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}
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return true;
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@ -14666,8 +14666,7 @@ cost_minus:
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*cost += extra_cost->alu.extend_arith;
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op1 = aarch64_strip_extend (op1, true);
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*cost += rtx_cost (op1, VOIDmode,
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(enum rtx_code) GET_CODE (op1), 0, speed);
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*cost += rtx_cost (op1, VOIDmode, GET_CODE (op1), 0, speed);
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return true;
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}
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@ -14678,9 +14677,7 @@ cost_minus:
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|| aarch64_shift_p (GET_CODE (new_op1)))
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&& code != COMPARE)
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{
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*cost += aarch64_rtx_mult_cost (new_op1, MULT,
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(enum rtx_code) code,
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speed);
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*cost += aarch64_rtx_mult_cost (new_op1, MULT, code, speed);
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return true;
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}
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@ -14781,8 +14778,7 @@ cost_plus:
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*cost += extra_cost->alu.extend_arith;
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op0 = aarch64_strip_extend (op0, true);
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*cost += rtx_cost (op0, VOIDmode,
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(enum rtx_code) GET_CODE (op0), 0, speed);
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*cost += rtx_cost (op0, VOIDmode, GET_CODE (op0), 0, speed);
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return true;
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}
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@ -14896,8 +14892,7 @@ cost_plus:
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&& aarch64_mask_and_shift_for_ubfiz_p (int_mode, op1,
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XEXP (op0, 1)))
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{
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*cost += rtx_cost (XEXP (op0, 0), int_mode,
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(enum rtx_code) code, 0, speed);
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*cost += rtx_cost (XEXP (op0, 0), int_mode, code, 0, speed);
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if (speed)
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*cost += extra_cost->alu.bfx;
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@ -14907,8 +14902,7 @@ cost_plus:
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{
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/* We possibly get the immediate for free, this is not
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modelled. */
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*cost += rtx_cost (op0, int_mode,
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(enum rtx_code) code, 0, speed);
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*cost += rtx_cost (op0, int_mode, code, 0, speed);
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if (speed)
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*cost += extra_cost->alu.logical;
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@ -14943,10 +14937,8 @@ cost_plus:
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}
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/* In both cases we want to cost both operands. */
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*cost += rtx_cost (new_op0, int_mode, (enum rtx_code) code,
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0, speed);
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*cost += rtx_cost (op1, int_mode, (enum rtx_code) code,
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1, speed);
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*cost += rtx_cost (new_op0, int_mode, code, 0, speed);
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*cost += rtx_cost (op1, int_mode, code, 1, speed);
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return true;
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}
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@ -14967,7 +14959,7 @@ cost_plus:
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/* MVN-shifted-reg. */
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if (op0 != x)
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{
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*cost += rtx_cost (op0, mode, (enum rtx_code) code, 0, speed);
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*cost += rtx_cost (op0, mode, code, 0, speed);
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if (speed)
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*cost += extra_cost->alu.log_shift;
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@ -14983,7 +14975,7 @@ cost_plus:
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rtx newop1 = XEXP (op0, 1);
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rtx op0_stripped = aarch64_strip_shift (newop0);
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*cost += rtx_cost (newop1, mode, (enum rtx_code) code, 1, speed);
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*cost += rtx_cost (newop1, mode, code, 1, speed);
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*cost += rtx_cost (op0_stripped, mode, XOR, 0, speed);
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if (speed)
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@ -15149,7 +15141,7 @@ cost_plus:
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&& known_eq (INTVAL (XEXP (op1, 1)),
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GET_MODE_BITSIZE (mode) - 1))
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{
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*cost += rtx_cost (op0, mode, (rtx_code) code, 0, speed);
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*cost += rtx_cost (op0, mode, code, 0, speed);
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/* We already demanded XEXP (op1, 0) to be REG_P, so
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don't recurse into it. */
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return true;
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@ -15212,7 +15204,7 @@ cost_plus:
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/* We can trust that the immediates used will be correct (there
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are no by-register forms), so we need only cost op0. */
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*cost += rtx_cost (XEXP (x, 0), VOIDmode, (enum rtx_code) code, 0, speed);
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*cost += rtx_cost (XEXP (x, 0), VOIDmode, code, 0, speed);
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return true;
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case MULT:
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@ -15402,12 +15394,11 @@ cost_plus:
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&& aarch64_vec_fpconst_pow_of_2 (XEXP (x, 1)) > 0)
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|| aarch64_fpconst_pow_of_2 (XEXP (x, 1)) > 0))
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{
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*cost += rtx_cost (XEXP (x, 0), VOIDmode, (rtx_code) code,
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0, speed);
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*cost += rtx_cost (XEXP (x, 0), VOIDmode, code, 0, speed);
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return true;
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}
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*cost += rtx_cost (x, VOIDmode, (enum rtx_code) code, 0, speed);
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*cost += rtx_cost (x, VOIDmode, code, 0, speed);
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return true;
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case ABS:
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@ -27369,13 +27360,13 @@ aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq,
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case E_SFmode:
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cmp_mode = SFmode;
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cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
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cc_mode = aarch64_select_cc_mode (code, op0, op1);
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icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf;
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break;
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case E_DFmode:
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cmp_mode = DFmode;
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cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
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cc_mode = aarch64_select_cc_mode (code, op0, op1);
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icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf;
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break;
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@ -27406,7 +27397,7 @@ aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq,
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*gen_seq = get_insns ();
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end_sequence ();
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return gen_rtx_fmt_ee ((rtx_code) code, cc_mode,
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return gen_rtx_fmt_ee (code, cc_mode,
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gen_rtx_REG (cc_mode, CC_REGNUM), const0_rtx);
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}
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@ -27443,12 +27434,12 @@ aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
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case E_SFmode:
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cmp_mode = SFmode;
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cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
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cc_mode = aarch64_select_cc_mode (cmp_code, op0, op1);
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break;
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case E_DFmode:
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cmp_mode = DFmode;
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cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
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cc_mode = aarch64_select_cc_mode (cmp_code, op0, op1);
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break;
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default:
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@ -27469,7 +27460,7 @@ aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
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end_sequence ();
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target = gen_rtx_REG (cc_mode, CC_REGNUM);
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aarch64_cond = aarch64_get_condition_code_1 (cc_mode, (rtx_code) cmp_code);
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aarch64_cond = aarch64_get_condition_code_1 (cc_mode, cmp_code);
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if (bit_code != AND)
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{
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@ -27508,7 +27499,7 @@ aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
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*gen_seq = get_insns ();
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end_sequence ();
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return gen_rtx_fmt_ee ((rtx_code) cmp_code, VOIDmode, target, const0_rtx);
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return gen_rtx_fmt_ee (cmp_code, VOIDmode, target, const0_rtx);
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}
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#undef TARGET_GEN_CCMP_FIRST
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