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aarch64: Optimise calls to ldexp with SVE FSCALE instruction [PR111733]
This patch uses the FSCALE instruction provided by SVE to implement the
standard ldexp family of functions.
Currently, with '-Ofast -mcpu=neoverse-v2', GCC generates libcalls for the
following code:
float
test_ldexpf (float x, int i)
{
return __builtin_ldexpf (x, i);
}
double
test_ldexp (double x, int i)
{
return __builtin_ldexp(x, i);
}
GCC Output:
test_ldexpf:
b ldexpf
test_ldexp:
b ldexp
Since SVE has support for an FSCALE instruction, we can use this to process
scalar floats by moving them to a vector register and performing an fscale call,
similar to how LLVM tackles an ldexp builtin as well.
New Output:
test_ldexpf:
fmov s31, w0
ptrue p7.b, vl4
fscale z0.s, p7/m, z0.s, z31.s
ret
test_ldexp:
sxtw x0, w0
ptrue p7.b, vl8
fmov d31, x0
fscale z0.d, p7/m, z0.d, z31.d
ret
This is a revision of an earlier patch, and now uses the extended definition of
aarch64_ptrue_reg to generate predicate registers with the appropriate set bits.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Soumya AR <soumyaa@nvidia.com>
gcc/ChangeLog:
PR target/111733
* config/aarch64/aarch64-sve.md
(ldexp<mode>3): Added a new pattern to match ldexp calls with scalar
floating modes and expand to the existing pattern for FSCALE.
* config/aarch64/iterators.md:
(SVE_FULL_F_SCALAR): Added an iterator to match all FP SVE modes as well
as their scalar equivalents.
(VPRED): Extended the attribute to handle GPF_HF modes.
* internal-fn.def (LDEXP): Changed macro to incorporate ldexpf16.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/fscale.c: New test.
This commit is contained in:
Soumya AR
parent
445d8bb6a8
commit
9b2915d95d
@ -5088,6 +5088,21 @@
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;; - FTSSEL
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;; -------------------------------------------------------------------------
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(define_expand "ldexp<mode>3"
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[(set (match_operand:GPF_HF 0 "register_operand")
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(unspec:GPF_HF
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[(match_dup 3)
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(const_int SVE_STRICT_GP)
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(match_operand:GPF_HF 1 "register_operand")
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(match_operand:<V_INT_EQUIV> 2 "register_operand")]
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UNSPEC_COND_FSCALE))]
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"TARGET_SVE"
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{
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operands[3] = aarch64_ptrue_reg (<VPRED>mode,
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GET_MODE_UNIT_SIZE (<MODE>mode));
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}
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)
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;; Unpredicated floating-point binary operations that take an integer as
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;; their second operand.
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(define_insn "@aarch64_sve_<optab><mode>"
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@ -5103,17 +5118,17 @@
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;; Predicated floating-point binary operations that take an integer
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;; as their second operand.
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(define_insn "@aarch64_pred_<optab><mode>"
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[(set (match_operand:SVE_FULL_F 0 "register_operand")
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(unspec:SVE_FULL_F
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[(set (match_operand:SVE_FULL_F_SCALAR 0 "register_operand")
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(unspec:SVE_FULL_F_SCALAR
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[(match_operand:<VPRED> 1 "register_operand")
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(match_operand:SI 4 "aarch64_sve_gp_strictness")
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(match_operand:SVE_FULL_F 2 "register_operand")
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(match_operand:SVE_FULL_F_SCALAR 2 "register_operand")
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(match_operand:<V_INT_EQUIV> 3 "register_operand")]
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SVE_COND_FP_BINARY_INT))]
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"TARGET_SVE"
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{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
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[ w , Upl , 0 , w ; * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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[ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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[ w , Upl , 0 , w ; * ] <sve_fp_op>\t%Z0.<Vetype>, %1/m, %Z0.<Vetype>, %Z3.<Vetype>
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[ ?&w , Upl , w , w ; yes ] movprfx\t%Z0, %Z2\;<sve_fp_op>\t%Z0.<Vetype>, %1/m, %Z0.<Vetype>, %Z3.<Vetype>
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}
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)
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@ -452,6 +452,9 @@
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;; All fully-packed SVE floating-point vector modes.
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(define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
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;; Fully-packed SVE floating-point vector modes and their scalar equivalents.
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(define_mode_iterator SVE_FULL_F_SCALAR [SVE_FULL_F GPF_HF])
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;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements.
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(define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI])
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@ -2354,7 +2357,8 @@
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(VNx8DI "VNx2BI") (VNx8DF "VNx2BI")
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(V8QI "VNx8BI") (V16QI "VNx16BI")
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(V4HI "VNx4BI") (V8HI "VNx8BI") (V2SI "VNx2BI")
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(V4SI "VNx4BI") (V2DI "VNx2BI") (V1DI "VNx2BI")])
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(V4SI "VNx4BI") (V2DI "VNx2BI") (V1DI "VNx2BI")
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(HF "VNx8BI") (SF "VNx4BI") (DF "VNx2BI")])
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;; ...and again in lower case.
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(define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi")
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@ -441,7 +441,7 @@ DEF_INTERNAL_OPTAB_FN (VEC_FMADDSUB, ECF_CONST, vec_fmaddsub, ternary)
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DEF_INTERNAL_OPTAB_FN (VEC_FMSUBADD, ECF_CONST, vec_fmsubadd, ternary)
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/* FP scales. */
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DEF_INTERNAL_FLT_FN (LDEXP, ECF_CONST, ldexp, binary)
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DEF_INTERNAL_FLT_FLOATN_FN (LDEXP, ECF_CONST, ldexp, binary)
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/* Ternary math functions. */
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DEF_INTERNAL_FLT_FLOATN_FN (FMA, ECF_CONST, fma, ternary)
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46
gcc/testsuite/gcc.target/aarch64/sve/fscale.c
Normal file
46
gcc/testsuite/gcc.target/aarch64/sve/fscale.c
Normal file
@ -0,0 +1,46 @@
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/* { dg-do compile } */
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/* { dg-additional-options "-Ofast" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** test_ldexpf16:
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** ...
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** ptrue (p[0-7]).b, vl2
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** ...
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** fscale z[0-9]+\.h, \1/m, z[0-9]+\.h, z[0-9]+\.h
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** ret
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*/
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_Float16
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test_ldexpf16 (_Float16 x, int i)
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{
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return __builtin_ldexpf16 (x, i);
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}
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/*
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** test_ldexpf:
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** ...
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** ptrue (p[0-7])\.b, vl4
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** ...
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** fscale z[0-9]+\.s, \1/m, z[0-9]+\.s, z[0-9]+\.s
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** ret
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*/
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float
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test_ldexpf (float x, int i)
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{
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return __builtin_ldexpf (x, i);
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}
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/*
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** test_ldexp:
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** ...
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** ptrue (p[0-7]).b, vl8
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** ...
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** fscale z[0-9]+\.d, \1/m, z[0-9]+\.d, z[0-9]+\.d
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** ret
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*/
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double
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test_ldexp (double x, int i)
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{
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return __builtin_ldexp (x, i);
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}
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