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hppa: Add peephole2 optimizations for REG+D loads and stores

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The PA 1.x architecture only supports long displacements in
integer loads and stores.  Floating-point loads and stores
only support short displacements.  As a result, we have to
wait until reload is complete before generating insns with
long displacements.

The PA 2.0 architecture supports long displacements in both
integer and floating-point loads and stores.

The peephole2 optimizations added in this change are only
enabled when 14-bit long displacements aren't supported for
floating-point loads and stores.

2024-09-18  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

	* config/pa/pa.h (GENERAL_REGNO_P): Define.
	* config/pa/pa.md: Add SImode and SFmode peephole2
	patterns to generate loads and stores with long
	displacements.
This commit is contained in:
John David Anglin 2024-09-18 11:02:32 -04:00
parent 85fcf74034
commit 4b03750f8c
2 changed files with 103 additions and 0 deletions
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3
gcc/config/pa/pa.h
View File

@ -480,6 +480,9 @@ extern rtx hppa_pic_save_rtx (void);
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS GENERAL_REGS
/* True if register is a general register. */
#define GENERAL_REGNO_P(N) ((N) >= 1 && (N) <= 31)
#define FP_REG_CLASS_P(CLASS) \
((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)

100
gcc/config/pa/pa.md
View File

@ -2280,6 +2280,58 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
; Rewrite RTL using a REG+D store. This will allow the insn that
; computes the address to be deleted if the register it sets is dead.
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(set (mem:SI (match_dup 0))
(match_operand:SI 3 "register_operand" ""))]
"!TARGET_64BIT
&& !INT14_OK_STRICT
&& GENERAL_REGNO_P (REGNO (operands[0]))
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
[(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
"")
; Rewrite RTL using a REG+D load. This will allow the insn that
; computes the address to be deleted if the register it sets is dead.
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (match_dup 0)))]
"!TARGET_64BIT
&& !INT14_OK_STRICT
&& GENERAL_REGNO_P (REGNO (operands[0]))
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) != REGNO (operands[3])
&& REGNO (operands[1]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
[(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(mem:SI (match_dup 0)))]
"!TARGET_64BIT
&& !INT14_OK_STRICT
&& GENERAL_REGNO_P (REGNO (operands[0]))
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) == REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
[(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2))))]
"")
; Rewrite RTL using an indexed store. This will allow the insn that
; computes the address to be deleted if the register it sets is dead.
(define_peephole2
@ -4507,6 +4559,54 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(set (mem:SF (match_dup 0))
(match_operand:SF 3 "register_operand" ""))]
"!TARGET_64BIT
&& !INT14_OK_STRICT
&& GENERAL_REGNO_P (REGNO (operands[0]))
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
[(set (mem:SF (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(set (match_operand:SF 3 "register_operand" "")
(mem:SF (match_dup 0)))]
"!TARGET_64BIT
&& !INT14_OK_STRICT
&& GENERAL_REGNO_P (REGNO (operands[0]))
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) != REGNO (operands[3])
&& REGNO (operands[1]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
[(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(set (match_operand:SF 3 "register_operand" "")
(mem:SF (match_dup 0)))]
"!TARGET_64BIT
&& !INT14_OK_STRICT
&& GENERAL_REGNO_P (REGNO (operands[0]))
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) == REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
[(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2))))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")