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AArch64: Define VECTOR_STORE_FLAG_VALUE.
This defines VECTOR_STORE_FLAG_VALUE to CONST1_RTX for AArch64 so we simplify vector comparisons in AArch64. With this enabled res: movi v0.4s, 0 cmeq v0.4s, v0.4s, v0.4s ret is simplified to: res: mvni v0.4s, 0 ret gcc/ChangeLog: * config/aarch64/aarch64.h (VECTOR_STORE_FLAG_VALUE): New. gcc/testsuite/ChangeLog: * gcc.dg/rtl/aarch64/vector-eq.c: New test.
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@ -156,6 +156,16 @@
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#define PCC_BITFIELD_TYPE_MATTERS 1
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/* Use the same RTL truth representation for vector elements as we do
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for scalars. This maintains the property that a comparison like
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eq:V4SI is a composition of 4 individual eq:SIs, just like plus:V4SI
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is a composition of 4 individual plus:SIs.
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This means that Advanced SIMD comparisons are represented in RTL as
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(neg (op ...)). */
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#define VECTOR_STORE_FLAG_VALUE(MODE) CONST1_RTX (GET_MODE_INNER (MODE))
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#ifndef USED_FOR_TARGET
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/* Define an enum of all features (ISA modes, architectures and extensions).
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29
gcc/testsuite/gcc.dg/rtl/aarch64/vector-eq.c
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29
gcc/testsuite/gcc.dg/rtl/aarch64/vector-eq.c
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@ -0,0 +1,29 @@
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/* { dg-do compile { target aarch64-*-* } } */
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/* { dg-additional-options "-O2" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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/*
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** foo:
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** mvni v0.4s, 0
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** ret
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*/
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__Uint32x4_t __RTL (startwith ("vregs")) foo (void)
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{
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(function "foo"
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(insn-chain
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(block 2
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(edge-from entry (flags "FALLTHRU"))
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(cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
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(cnote 2 NOTE_INSN_FUNCTION_BEG)
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(cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))
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(cinsn 4 (set (reg:V4SI <1>) (reg:V4SI <0>)))
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(cinsn 5 (set (reg:V4SI <2>)
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(neg:V4SI (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>)))))
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(cinsn 6 (set (reg:V4SI v0) (reg:V4SI <2>)))
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(edge-to exit (flags "FALLTHRU"))
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)
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)
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(crtl (return_rtx (reg/i:V4SI v0)))
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)
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}
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