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RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander
The comment previously here stated that the Wc0/Wc1 cases are handled by the vi constraint but that is not true for the 0.0 Wc0 case. gcc/ChangeLog: * config/riscv/riscv-v.h (valid_vec_immediate_p): Add new helper. * config/riscv/riscv-v.cc (valid_vec_immediate_p): Ditto. (expand_const_vector): Use new helper. * config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point case. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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@ -794,6 +794,15 @@ const_vec_all_in_range_p (rtx vec, poly_int64 minval, poly_int64 maxval)
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return true;
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}
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/* Returns true if the vector's elements are all duplicates in
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range -16 ~ 15 integer or 0.0 floating-point. */
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bool
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valid_vec_immediate_p (rtx x)
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{
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return (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x));
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}
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/* Return a const vector of VAL. The VAL can be either const_int or
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const_poly_int. */
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@ -1119,7 +1128,7 @@ expand_const_vector (rtx target, rtx src)
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{
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/* Element in range -16 ~ 15 integer or 0.0 floating-point,
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we use vmv.v.i instruction. */
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if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src))
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if (valid_vec_immediate_p (src))
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{
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rtx ops[] = {result, src};
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emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
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@ -83,6 +83,8 @@ private:
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unsigned int m_inner_bytes_size;
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};
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extern bool valid_vec_immediate_p(rtx);
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} // namespace riscv_vector
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#endif // GCC_RISCV_V_H
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@ -2158,11 +2158,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
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if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
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&& !immediate_operand (elt, Pmode))
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return 0;
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/* Constants from -16 to 15 can be loaded with vmv.v.i.
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The Wc0, Wc1 constraints are already covered by the
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vi constraint so we do not need to check them here
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separately. */
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if (satisfies_constraint_vi (x))
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/* Constants in range -16 ~ 15 integer or 0.0 floating-point
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can be emitted using vmv.v.i. */
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if (valid_vec_immediate_p (x))
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return 1;
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/* Any int/FP constants can always be broadcast from a
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